This page intentionally left blank | Intel IQ80321 specification

Intel® IQ80321 I/O Processor Evaluation Platform

Contents

This page intentionally left blank.

12	Board Manual

Image 12

Intel IQ80321 manual This page intentionally left blank

Contents

Intel IQ80321 I/O Processor Evaluation Platform Board Manual Intel IQ80321 I/O Processor Evaluation Platform Board Manual Contents Debug Interface Dram 100 119 Figures Tables 105 Revision History Description This page intentionally left blank Document Purpose and Scope Related Documents Electronic Information Component ReferencesElectronic Information Component Reference Terms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Block Diagram Intel 80321 I/O Processor Intel IQ80321 I/O Processor Evaluation Platform Intel IQ80321 Evaluation Platform Board Features Summary of FeaturesFeature Definition Kit Content Hardware InstallationFirst-Time Installation and Test Power and Backplane Requirements Factory Settings Contents of the FlashDevelopment Strategy Supported Tool Buckets Redhat Redboot Target Monitors ARM Firmware Suite ARM Angel Semihosting File I/O Host Communications Examples Serial-UART CommunicationEthernet-Network Communication Jtag Debug Communication Jtag Debug Communication Communicating with Redboot GNUPro GDB/Insight Intel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaud ARM Extended Debugger This page intentionally left blank Functional Diagram Intel Form-Factor/Connectivity Features Board Form-Factor/Connectivity Power Power Features Battery Backup DDR Memory FeaturesMemory Subsystem Supported Dimm Types Flash Memory Requirements Flash Memory Requirements Intel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O Processor Peripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral Bus Flash ROM Features Flash ROM Uart Features Uart HEX Display HEX Display on the Peripheral Bus Rotary Switch Rotary Switch Requirements Battery Status Battery Status Buffer Requirements Debug Interface Console Serial PortEthernet Port Intel 82544EI Gigabit Ethernet Controller Logic-Analyzer Connectors Jtag Debug3.1 Jtag Port Jtag Port Pin-out Micor J3F2 Signal/Pins Mictor J3F2 Micor J2F1 Signal/Pins Schematic Signal NameMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1 Micor J3C1 Signal/Pins Mictor J3C1 Micor J2C1 Signal/Pins Mictor J2C1 Board Reset Scheme Reset Requirements/SchemesReset Sources Switches and Jumpers Switch Summary User Defined Switches PCI-X Bridge Initialization SignalsPcix Initialization Summary Default Switch Settings Visual Connector Summary Jumper SummaryGeneral Purpose Input/Output Header Secondary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Detail Descriptions of Switches/Jumpers Switch S7E1- 2/3 Switch S7E1- 4/5 Switch S7E1- 6/7 Switch S7E1 Switch S7E1 8 DescriptionsSwitch S7E1 8 Settings and Operation Mode S7E1-8 Switch S8E1 Switch S8E1 5 Descriptions Switch S8E1 5 Settings and Operation ModeSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 Descriptions Switch S8E1 7 Descriptions Switch S8E1 7 Settings and Operation ModeSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation Mode Switch S8E2 1/2 Switch S8E2 Switch S9E1 Switch S9E1 13 DescriptionsSwitch S9E1 13 Settings and Operation Mode Switch S9E1 4 Descriptions Switch S1D1 1/2 Switch S4D1 1/2Switch S4D1 3/4 Jumper J1G2 Jumper J3E1Jumper J3G1 Jumper J9E1 Jumper J9F1 This page intentionally left blank Private Device Configuration Private Device Configuration RequirementsIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device Dram Components on the Peripheral BusDDR Memory Bias Voltage Minimum/Maximum Values Parameter Voltages Software Reference Uart Register Settings Address Read Register Write Register Hex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Board Support Package BSP Examples Intel 80321 I/O Processor Memory MapIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range Description Redboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Introduction PurposeNecessary Hardware and Software Related Web Sites Setup Hardware Setup Software Setup Software Flow Diagram New Project Setup Creating a New Project Configuration Flashing with Jtag Overview Using Flash Programmer Debugging Out of Flash Building an Executable File From Example Code Launching and Configuring Debugger Running the CodeLab Debugger Manually Loading and Executing an Application Program Displaying Source Code Using Breakpoints Setting CodeLab Debug Options Stepping Through the Code Exploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware Breakpoints Exceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping