Jtag Debug Communication | Intel IQ80321 manual

Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started

2.6.3JTAG Debug Communication

Using a JTAG Emulator:

Figure 4. JTAG Debug Communication

Host System

SW Debugger

C/C++

ASMEmulator

JTAG

Parallel

Port

Host System

JTAG

Connector

Intel® 80321

I/O Processor

Running a

Debug Monitor

Intel® IQ80321 Evaluation Platform Board

PCI/PCI-X Platform

Server/Desktop/Backplane

A9649-01

Board Manual

25

Image 25

Intel IQ80321 manual Jtag Debug Communication

Contents

Board Manual Intel IQ80321 I/O Processor Evaluation Platform Board Manual Intel IQ80321 I/O Processor Evaluation Platform Contents Debug Interface Dram 100 119 Figures Tables 105 Description Revision History This page intentionally left blank Related Documents Document Purpose and Scope Component References Electronic InformationElectronic Information Component Reference Terms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Intel 80321 I/O Processor Block Diagram Intel IQ80321 I/O Processor Evaluation Platform Summary of Features Intel IQ80321 Evaluation Platform Board FeaturesFeature Definition Hardware Installation Kit ContentFirst-Time Installation and Test Power and Backplane Requirements Contents of the Flash Factory SettingsDevelopment Strategy Supported Tool Buckets Target Monitors Redhat Redboot ARM Firmware Suite Semihosting File I/O ARM Angel Serial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug Communication GNUPro GDB/Insight Communicating with Redboot Intel IQ80321 I/O Processor Evaluation Platform GDB set remotebaud Connecting with GDB ARM Extended Debugger This page intentionally left blank Intel Functional Diagram Board Form-Factor/Connectivity Form-Factor/Connectivity Features Power Features Power DDR Memory Features Battery BackupMemory Subsystem Supported Dimm Types Flash Memory Requirements Flash Memory Requirements Intel 80321 I/O Processor Operation Mode 80321 I/O Processor Interrupt Routing Intel IQ80321 Evaluation Platform Board Peripheral Bus Peripheral Bus Features Flash ROM Flash ROM Features Uart Uart Features HEX Display on the Peripheral Bus HEX Display Rotary Switch Requirements Rotary Switch Battery Status Buffer Requirements Battery Status Console Serial Port Debug InterfaceEthernet Port Intel 82544EI Gigabit Ethernet Controller Jtag Debug Logic-Analyzer Connectors3.1 Jtag Port Jtag Port Pin-out Mictor J3F2 Micor J3F2 Signal/Pins Schematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Mictor J1C1 Micor J1C1 Signal/Pins Mictor J3C1 Micor J3C1 Signal/Pins Mictor J2C1 Micor J2C1 Signal/Pins Reset Requirements/Schemes Board Reset SchemeReset Sources Switch Summary Switches and Jumpers PCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Switch S7E1- 2/3 Detail Descriptions of Switches/Jumpers Switch S7E1- 6/7 Switch S7E1- 4/5 Switch S7E1 8 Descriptions Switch S7E1Switch S7E1 8 Settings and Operation Mode S7E1-8 Switch S8E1 Switch S8E1 5 Settings and Operation Mode Switch S8E1 5 DescriptionsSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 Descriptions Switch S8E1 7 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation Mode Switch S8E2 Switch S8E2 1/2 Switch S9E1 13 Descriptions Switch S9E1Switch S9E1 13 Settings and Operation Mode Switch S9E1 4 Descriptions Switch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9F1 Jumper J9E1 This page intentionally left blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device Configuration Components on the Peripheral Bus DramDDR Memory Bias Voltage Minimum/Maximum Values Parameter Voltages Software Reference Address Read Register Write Register Uart Register Settings Hex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Physical Address Range Description Redboot* Intel IQ80321 Memory Map Redboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Purpose IntroductionNecessary Hardware and Software Related Web Sites Hardware Setup Setup Software Flow Diagram Software Setup Creating a New Project New Project Setup Configuration Overview Flashing with Jtag Using Flash Programmer Building an Executable File From Example Code Debugging Out of Flash Running the CodeLab Debugger Launching and Configuring Debugger Displaying Source Code Manually Loading and Executing an Application Program Using Breakpoints Stepping Through the Code Setting CodeLab Debug Options Exploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Hardware and Software Breakpoints Debugging BasicsSoftware Breakpoints Hardware Breakpoints Exceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping