Intel® IQ80321 I/O Processor Evaluation Platform

Hardware Reference Section

3.10.9.5Switch S8E1- 2

Turn On to enable on-board Gigabit Ethernet, otherwise Off for better PCI-X loading/performance.

Table 47.

Switch S8E1 - 2: Descriptions

 

 

 

 

 

 

 

Switch

Association

Description

Factory Default

 

 

 

 

 

 

S8E1-2

SPCI-X Bus

QSWITCHEN: Quick-Switch to make GbE NIC visible

On

 

on the SPCI-X bus.

 

 

 

 

 

 

 

 

 

Table 48.

Switch S8E1 - 2: Settings and Operation Mode

 

S8E1-2

Operation Mode

 

 

 

 

Off

82544EI Isolated from secondary PCI-X bus.

 

 

 

 

On

82544EI Included on as a device on the secondary PCI-X bus.

 

 

 

3.10.9.6Switch S8E1- 3

Close to enable bridge to be the arbiter.

Table 49.

Switch S8E1 - 3: Descriptions

 

 

 

 

 

 

 

Switch

Association

Description

Factory Default

 

 

 

 

 

 

S8E1-3

PCI-X Bridge

S_INT_ARB_EN: Internal bridge arbiter operation.

On

 

 

 

 

 

Table 50.

Switch S8E1 - 3: Settings and Operation Mode

 

 

 

 

 

 

 

S8E1-3

 

Operation Mode

 

 

 

 

 

 

Off

Disable internal bridge arbiter, use external arbiter.

 

 

 

 

 

 

On

Use internal arbiter.

 

 

 

 

 

 

3.10.9.7Switch S8E1- 4

Used to choose between 100 MHz and 133 MHz maximum operating frequency on the secondary interface when in the PCI-X mode. It has no meaning in the PCI mode.

When the bridge initially samples a b’1’ value on the S_PCIXCAP input, then all clients on the bus are capable of PCI-X 133 operation. The bridge then samples the S_SEL100 input to distinguish between the 66-100 MHz and the 100-133 MHz clock frequency ranges. When it detects a b’1’ value on the S_SEL100 input, the bus is initialized with the PCI-X 100 initialization pattern. When the value is b’0’, the PCI-X 133 initialization pattern is used. These two ranges allow adjustment of the clock frequency to account for bus loading conditions.

Since the internal PLL is bypassed in the PCI mode and the S_CLK input is used directly, the IBM 133 PCI-X Bridge R2.0 has no need to distinguish between the PCI 66 and PCI 33 modes. Therefore the bridge does not have an I/O pin for the M66EN signal on its secondary interface.

Table 51.

Switch S8E1 - 4: Descriptions

 

 

 

 

 

 

 

Switch

Association

Description

Factory Default

 

 

 

 

 

 

S8E1-4

PCI-X Bridge

S_SEL100: SPCI-X max operation frequency indictor.

Off

 

 

 

 

 

Table 52.

Switch S8E1 - 4: Settings and Operation Mode

 

 

 

 

 

 

 

S8E1-4

 

Operation Mode

 

 

 

 

 

 

 

Off

1: 100 MHz.

 

 

 

 

 

 

 

 

On

0: 133 MHz.

 

 

 

 

 

 

 

60

Board Manual

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Image 60
Intel IQ80321 manual Switch S8E1