106 | Intel IQ80321 instruction

Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started and Debugger

C.1.4 Related Web Sites

•Macraigor: http://www.ocdemon.net/

•http://developer.intel.com/design/intelxscale/dev_tools/020523/index.htm

•http://developer.intel.com/design/iio/80321.htm

•http://developer.intel.com/design/iio/docs/iop321.htm

•http://developer.intel.com/design/iio/swsup/Tester321LED.htm

106	Board Manual

Image 106

Intel IQ80321 manual 106

Contents

Intel IQ80321 I/O Processor Evaluation Platform Board Manual Intel IQ80321 I/O Processor Evaluation Platform Board Manual Contents Debug Interface Dram 100 119 Figures Tables 105 Revision History Description This page intentionally left blank Document Purpose and Scope Related Documents Electronic Information Electronic InformationComponent References Component Reference Terms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Block Diagram Intel 80321 I/O Processor Intel IQ80321 I/O Processor Evaluation Platform Summary of Features Intel IQ80321 Evaluation Platform Board FeaturesFeature Definition First-Time Installation and Test Kit ContentHardware Installation Power and Backplane Requirements Development Strategy Factory SettingsContents of the Flash Supported Tool Buckets Redhat Redboot Target Monitors ARM Firmware Suite ARM Angel Semihosting File I/O Serial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug Communication Communicating with Redboot GNUPro GDB/Insight Intel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaud ARM Extended Debugger This page intentionally left blank Functional Diagram Intel Form-Factor/Connectivity Features Board Form-Factor/Connectivity Power Power Features Memory Subsystem Battery BackupDDR Memory Features Supported Dimm Types Flash Memory Requirements Flash Memory Requirements Intel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O Processor Peripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral Bus Flash ROM Features Flash ROM Uart Features Uart HEX Display HEX Display on the Peripheral Bus Rotary Switch Rotary Switch Requirements Battery Status Battery Status Buffer Requirements Ethernet Port Debug InterfaceConsole Serial Port Intel 82544EI Gigabit Ethernet Controller 3.1 Jtag Port Logic-Analyzer ConnectorsJtag Debug Jtag Port Pin-out Micor J3F2 Signal/Pins Mictor J3F2 Schematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1 Micor J3C1 Signal/Pins Mictor J3C1 Micor J2C1 Signal/Pins Mictor J2C1 Reset Requirements/Schemes Board Reset SchemeReset Sources Switches and Jumpers Switch Summary PCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Detail Descriptions of Switches/Jumpers Switch S7E1- 2/3 Switch S7E1- 4/5 Switch S7E1- 6/7 Switch S7E1 8 Settings and Operation Mode Switch S7E1Switch S7E1 8 Descriptions S7E1-8 Switch S8E1 Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 6 Descriptions Switch S8E1 8 Descriptions Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Settings and Operation Mode Switch S8E2 1/2 Switch S8E2 Switch S9E1 13 Settings and Operation Mode Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 4 Descriptions Switch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9E1 Jumper J9F1 This page intentionally left blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device DDR Memory Bias Voltage Minimum/Maximum Values DramComponents on the Peripheral Bus Parameter Voltages Software Reference Uart Register Settings Address Read Register Write Register Hex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range Description Redboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Purpose IntroductionNecessary Hardware and Software Related Web Sites Setup Hardware Setup Software Setup Software Flow Diagram New Project Setup Creating a New Project Configuration Flashing with Jtag Overview Using Flash Programmer Debugging Out of Flash Building an Executable File From Example Code Launching and Configuring Debugger Running the CodeLab Debugger Manually Loading and Executing an Application Program Displaying Source Code Using Breakpoints Setting CodeLab Debug Options Stepping Through the Code Exploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Software Breakpoints Debugging BasicsHardware and Software Breakpoints Hardware Breakpoints Exceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping