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Company X Accessories C1030-5510 manual LEDs, HEX rotary DIP switch

Models: C1030-5510

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configurable LEDs allow to make internal monitoring status signals visible by driving the appropriate FPGA IO to a HIGH level.

Figure 4: Bitte durch Orginalbild ersetzen

LEDs

Signal Name	FPGA IO	Comment

SYS_LED0	--	Internal 5V power supply.
SYS_LED1	--	Power OK- signal from onboard voltage regulator.
SYS_LED2	V17	Illuminates to indicate the status of the DONE pin if FPGA is
		successfully configured.
USER_LED0	P7	User- configurable LED.
USER_LED1	N7	User- configurable LED.
USER_LED2	P8	User- configurable LED.
USER_LED3	N6	User- configurable LED.
USER_LED4	R7	User- configurable LED.

The HEX rotary DIP switch is of binary coded type. The four weighted terminals are externally pulled HIGH with 4,7 kOhm resistors, the common terminals are connected to GND. Therefore the four FPGA inputs behave like a complementary binary coded hexadecimal switch.

	HEX rotary DIP switch
	DIAL	FPGA Pin N8	FPGA Pin M11	FPGA Pin M10	FPGA Pin N9
	0	1	1	1	1
	1	0	1	1	1
	2	1	0	1	1
	3	0	0	1	1
	4	1	1	0	1

USBS6 / C1030-5510					http://www.cesys.com/
User Doc V0.3			-12-		preliminary

Image 12

Company X Accessories C1030-5510 manual LEDs, HEX rotary DIP switch, Fpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9

Contents

USBS6 June 29 Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Powering USBS6 Bus- powered USB is used as power supply input 3V@ ??? mAModes of operation Mode Configuration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5 MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10G HEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connector ADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designs FX-2/FPGA slave Fifo connection Introduction to example Fpga designs ISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/usbs6soctop.vhd Src/wbintercon.vhdSrc/wbmafx2.vhd Src/wbslbram.vhd Src/wbslmcb.vhd Src/wbsluart.vhdSrc/xiluartmacro Src/xilmcbmig Signals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slaves Design usbs6bram Example Src/usbs6bramtop.vhd Src/simtb/wbslbramtb.vhdUsbs6bram.xise Usbs6bram.ucf Wbslbramtb.cmd Introduction Changes to previous versions Driver installation WindowsRequirements Build UDK Lets assume to use c\\udkapi Linux Drivers PCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK build API Error handling API Functions in detail++ and .NET API GetLastErrorCode Error code Kind of errorGetLastErrorText Methods/Functions Device enumeration InitDeInit Enumerate DeviceType DescriptionGetDeviceCount Static unsigned int ceDeviceGetDeviceCount GetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdx Information gathering GetUDKVersionStringGetDeviceUID GetDeviceName GetBusType Constant BusGetMaxTransferSize Using devices OpenClose Void ceDeviceOpen ReadRegister WriteRegisterReadBlock WriteBlock EnableInterrupt ResetFPGAWaitForInterrupt SetTimeOut ProgramFPGAFromBINProgramFPGAFromMemory ProgramFPGAFromMemoryZ EnableBurst Void ceDeviceEnableBurstbool bEnable UDKLab Introduction Main screen UDKLab Main Screen Using UDKLab Device selection flow Fpga configuration Prepare to work with device Fpga design flashing Projects Sequence contents Add new initializing task Content panel Sequence start Register entry Register panel Data area entry Data area panel Using SPI-Flash for configuration How to store configuration data in SPI-Flash M25P16 Fpga Connection Jtag Signal Name IO pairing and etch length report J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUTNet name Direction 52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28 Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mm Table of contents Table of Contents USB PCI ++ API