Build UDK | Company X Accessories C1030-5510 manual

Build drivers:

cd PlxSdk/Linux/Driver

PLX_SDK_DIR=`pwd`/../../ ./buildalldrivers

Loading the driver manually requires a successful build, it is done using the following commands:

cd ~/udkapi2.0/drivers/linux/PlxSdk sudo PLX_SDK_DIR=`pwd` Bin/Plx_load Svc

PCI based boards like the PCIS3Base require the following driver:

sudo PLX_SDK_DIR=`pwd` Bin/Plx_load 9056

PCIe based boards like the PCIeV4Base require the following:

sudo PLX_SDK_DIR=`pwd` Bin/Plx_load 8311

Automation of this load process is out of the scope of this document.

Build UDK

Prerequisites

The whole UDK will be build using CMake, a free cross platform build tool. It creates dynamic Makefiles on unix compatible platforms.

The first thing should be editing the little configuration file linux.cmake inside the installation root of the UDK. It contains the following options:

•BUILD_UI_TOOLS If 0 UDKLab isn't build, if 1 UDKLab is part of the build, but requires a compatible wxWidgets installation.

•CMAKE_BUILD_TYPE Select build type, can be one of Debug, Release, RelWithDebInfo, MinSizeRel. If there should be at least 2 builds in parallel, remove this line and specify the type using command line option -DCMAKE_BUILD_TYPE=….

Makefile creation and build

Best usage is to create an empty build directory and run cmake inside of it:

cd ~/udkapi2.0 mkdir build cd build cmake ..

If all external dependencies are met, this will finish creating a Makefile. To build the UDK, just invoke make:

make

Important: The UDK C++ API must be build with the same toolchain and build flags like

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-35-	preliminary

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Company X Accessories C1030-5510 manual Build UDK, Makefile creation and build

Contents

June 29 USBS6 Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operation Name ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller Lpddr Sdram MT46H64M16LFCK-5 External memory MCB1DQ0 SPI Flash MX25L12845EMI-10G Peripherals Fpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4 ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basics Introduction to example Fpga designs FX-2/FPGA slave Fifo connection ISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhd Src/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacro Signals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the master Example Design usbs6bram Usbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xise Wbslbramtb.cmd Changes to previous versions Introduction Build UDK Driver installationWindows Requirements Lets assume to use c\\udkapi Drivers Linux PCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projects ++ and .NET API API Error handlingAPI Functions in detail Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorText DeInit Device enumerationInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCount Static ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDevice GetDeviceName Information gatheringGetUDKVersionString GetDeviceUID GetMaxTransferSize GetBusTypeConstant Bus Void ceDeviceOpen Using devicesOpen Close WriteBlock ReadRegisterWriteRegister ReadBlock WaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemory Void ceDeviceEnableBurstbool bEnable EnableBurst Introduction UDKLab UDKLab Main Screen Main screen Device selection flow Using UDKLab Prepare to work with device Fpga configuration Projects Fpga design flashing Sequence contents Add new initializing task Sequence start Content panel Register panel Register entry Data area panel Data area entry How to store configuration data in SPI-Flash Using SPI-Flash for configuration M25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name 52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Addio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensions Table of contents Table of Contents USB PCI ++ API