incremented automatically in block transfers. You can find details on enabling/disabling the burst mode and address
CESYS USB transfer protocol is converted into one or more WISHBONE data transaction cycles. So the
WISHBONE signals driven by the master:
•STB_O: strobe, qualifier for the other output signals of the master, indicates valid data and control signals
•WE_O: write enable, indicates, if a write or read cycle is in progress
•ADR_O[31:2]:
•DAT_O[31:0]:
WISHBONE signals driven by slaves:
•DAT_I[31:0]:
•ACK_I: handshake signal, slave devices indicate a successful data transfer for writing and valid data on bus for reading by asserting this signal, slaves can insert wait states by delaying this signal, it is possible to assert ACK_I in first clock cycle of STB_O assertion using a combinatorial handshake to transfer data in one clock cycle (recommendation: registered feedback handshake should be used in applications, where maximum data throughput is not needed, because timing specs are easier to meet)
USBS6 / |
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User Doc V0.3 | preliminary |