Company X Accessories C1030-5510 Src/usbs6bramtop.vhd, Src/simtb/wbslbramtb.vhd, Usbs6bram.xise

WISHBONE cycles. It is a reduced version of “usbs6_soc” example implementing a single BlockRAM slave.

Files and modules

src/wishbone_pkg.vhd:

See chapter “Design usbs6_soc”

src/usbs6_bram_top.vhd:

This is the top level module. It instantiates FX-2 module as a WISHBONE master device (wb_ma_fx2.vhd) and a BlockRAM as a WISHBONE slave device (wb_sl_bram.vhd).

src/wb_ma_fx2.vhd:

See chapter “Design usbs6_soc”

src/wb_sl_bram.vhd:

See chapter “Design usbs6_soc”

src/sim_tb/wb_sl_bram_tb.vhd:

Example of a VHDL simulation testbench demonstrating BFM techniques for accessing BlockRAM as a WISHBONE slave device (wb_sl_bram.vhd).

src/fx2_slfifo_ctrl.vhd:

See chapter “Design usbs6_soc”

src/sync_fifo.vhd:

See chapter “Design usbs6_soc”

usbs6_bram.xise:

Project file for XilinxTM ISE.

usbs6_bram.ucf:

User constraint file with timing and pinout constraints.

wb_sl_bram_tb.do:

ModelSim command macro file for BFM BlockRAM testbench (wb_sl_bram_tb.vhd).

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