Prepare to work with device | Company X Accessories C1030-5510

After a device has been selected, most UI components are available:

•FPGA configuration

•FPGA design flashing [if device has support]

•Project controls

•Initializer controls (Related to projects)

The last disabled component at this point is the content panel. It is enabled if the initialization sequence has been run. The complete flow to enable all UI elements can be seen below:

Figure 13: Prepare to work with device

FPGA configuration

Choosing this will pop up a file selection dialog, allowing to choose the design for download. If the file choosing isn't canceled, the design will be downloaded subsequent to closing the dialog.

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-53-	preliminary

Image 53

Company X Accessories C1030-5510 manual Prepare to work with device, Fpga configuration

Contents

June 29 USBS6 Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Bus- powered USB is used as power supply input 3V@ ??? mA Powering USBS6Modes of operation Mode Name ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller Lpddr Sdram MT46H64M16LFCK-5 External memory MCB1DQ0 SPI Flash MX25L12845EMI-10G Peripherals Fpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4 ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basics Introduction to example Fpga designs FX-2/FPGA slave Fifo connection ISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbintercon.vhd Src/usbs6soctop.vhdSrc/wbmafx2.vhd Src/wbslbram.vhd Src/wbsluart.vhd Src/wbslmcb.vhdSrc/xiluartmacro Src/xilmcbmig Signals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the master Example Design usbs6bram Src/simtb/wbslbramtb.vhd Src/usbs6bramtop.vhdUsbs6bram.xise Usbs6bram.ucf Wbslbramtb.cmd Changes to previous versions Introduction Windows Driver installationRequirements Build UDK Lets assume to use c\\udkapi Drivers Linux PCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projects ++ and .NET API API Error handlingAPI Functions in detail Error code Kind of error GetLastErrorCodeGetLastErrorText Methods/Functions DeInit Device enumerationInit DeviceType Description EnumerateGetDeviceCount Static unsigned int ceDeviceGetDeviceCount Static ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDevice GetUDKVersionString Information gatheringGetDeviceUID GetDeviceName GetMaxTransferSize GetBusTypeConstant Bus Open Using devicesClose Void ceDeviceOpen WriteRegister ReadRegisterReadBlock WriteBlock WaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromBIN SetTimeOutProgramFPGAFromMemory ProgramFPGAFromMemoryZ Void ceDeviceEnableBurstbool bEnable EnableBurst Introduction UDKLab UDKLab Main Screen Main screen Device selection flow Using UDKLab Prepare to work with device Fpga configuration Projects Fpga design flashing Sequence contents Add new initializing task Sequence start Content panel Register panel Register entry Data area panel Data area entry How to store configuration data in SPI-Flash Using SPI-Flash for configuration M25P16 Fpga Connection Jtag Signal Name J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT IO pairing and etch length reportNet name Direction 52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Addio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensions Table of contents Table of Contents USB PCI ++ API