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Company X Accessories C1030-5510 manual Sequence start, Content panel

Models: C1030-5510

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Sequence start

The button sitting below the list runs all actions from top to bottom. In addition to this, the remaining UI components, the content panel, will be enabled, as UDKLab expects a working communication at this point. The sequence can be modified an started as often as wished.

Content panel

The content panel can be a visual representation of the FPGA design loaded during initialization. It consists of a list of registers and data areas, which can be visit and modified using UDKLab. The view is split into two columns, while the left part contains the registers and the right part all data area / block entries.

Figure 17: Content panel

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-57-	preliminary

Image 57

Company X Accessories C1030-5510 manual Sequence start, Content panel

Contents

June 29 USBS6 Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Bus- powered USB is used as power supply input 3V@ ??? mA Powering USBS6Modes of operation Mode Configuration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memory MCB1DQ0 SPI Flash MX25L12845EMI-10G Peripherals HEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4 ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basics Introduction to example Fpga designs FX-2/FPGA slave Fifo connection ISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/wbintercon.vhd Src/usbs6soctop.vhdSrc/wbmafx2.vhd Src/wbslbram.vhd Src/wbsluart.vhd Src/wbslmcb.vhdSrc/xiluartmacro Src/xilmcbmig Signals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the master Example Design usbs6bram Src/simtb/wbslbramtb.vhd Src/usbs6bramtop.vhdUsbs6bram.xise Usbs6bram.ucf Wbslbramtb.cmd Changes to previous versions Introduction Windows Driver installationRequirements Build UDK Lets assume to use c\\udkapi Drivers Linux PCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projects API Error handling API Functions in detail++ and .NET API Error code Kind of error GetLastErrorCodeGetLastErrorText Methods/Functions Device enumeration InitDeInit DeviceType Description EnumerateGetDeviceCount Static unsigned int ceDeviceGetDeviceCount Static ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDevice GetUDKVersionString Information gatheringGetDeviceUID GetDeviceName GetBusType Constant BusGetMaxTransferSize Open Using devicesClose Void ceDeviceOpen WriteRegister ReadRegisterReadBlock WriteBlock EnableInterrupt ResetFPGAWaitForInterrupt ProgramFPGAFromBIN SetTimeOutProgramFPGAFromMemory ProgramFPGAFromMemoryZ Void ceDeviceEnableBurstbool bEnable EnableBurst Introduction UDKLab UDKLab Main Screen Main screen Device selection flow Using UDKLab Prepare to work with device Fpga configuration Projects Fpga design flashing Sequence contents Add new initializing task Sequence start Content panel Register panel Register entry Data area panel Data area entry How to store configuration data in SPI-Flash Using SPI-Flash for configuration M25P16 Fpga Connection Jtag Signal Name J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT IO pairing and etch length reportNet name Direction 52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Addio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensions Table of contents Table of Contents USB PCI ++ API