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In FPGA designs with multiple clock domains asynchronous FIFOs have to be used for transferring data from one clock domain to the other and comprehensive control signals have to be resynchronized.
Other clock sources can be added internally by using
FX-2/FPGA slave FIFO connection
Only the logical behavior of slave FIFO interface is discussed here. For information about the timing behavior like setup- and
All flags and control signals are active low (postfix “#”). The whole interface is synchronous to IFCLK. The asynchronous FIFO transfer mode is not supported.
•SLWR#:
•SLRD#:
•SLOE#:
•PKTEND#:
•Short packets sometimes lead to unpredictable behavior at host side. So CESYS USB cards do not support short packets! This signal has to be statically set to HIGH! Dummy data should be added instead of creating short packets. There is normally no lack of performance by doing this, because transmission of USB packets is bound to a time framing scheme, regardless of amount of payload data.
•FIFOADR[1:0]:
•Switching FIFOADR[1] is enough to select data direction. FIFOADR[0] has to be statically set to LOW!
•
•FD[15:0]: bidirectional tristate data bus
Introduction to example FPGA designs
The CESYS USBS6 Card is shipped with some demonstration FPGA designs to give you an easy starting point for own development projects. The whole source code is written in
USBS6 / |
| http://www.cesys.com/ |
User Doc V0.3 | preliminary |