Company X Accessories C1030-5510 manual Src/usbs6soctop.vhd, Src/wbintercon.vhd, Src/wbmafx2.vhd

(BFM), too. These can be used for behavioral simulation purposes.

src/usbs6_soc_top.vhd:

This is the top level entity of the design. The WISHBONE components are instantiated here.

src/wb_intercon.vhd:

All WISHBONE devices are connected to this shared bus interconnection logic. Some MSBs of the address are used to select the appropriate slave.

src/wb_ma_fx2.vhd:

This is the entity of the WISHBONE master, which converts the CESYS USB protocol into one or more 32 Bit single read/write WISHBONE cycles. The low level FX-2 slave FIFO controller (fx2_slfifo_ctrl.vhd) is used and 16/32 bit data width conversion is done by using special FIFOs (sfifo_hd_a1Kx18b0K5x36.vhd).

src/wb_sl_bram.vhd:

A internal BlockRAM is instantiated here and simply connected to the WISHBONE architecture. It can be used for testing address oriented data transactions over USB.

src/wb_sl_gpio.vhd:

This entity provides up to 256 general purpose I/Os to set and monitor non-timing-critical internal and external FPGA signals. The I/Os can be accessed as eight ports with 32 bits each. Every single I/O can be configured as an in- or output.

I/O signals of VG96 connector VG96_IO[80:0] are at port0 – port2, bits[80:0], I/O signals of add-on connector ADD_IO[33:0] are at port3 – port4, bits[129:96], user LEDs are at port5, bits[163:160] and hex encoder is at port6, bits[195:192].

Port7 is used for monitoring MCB status signals bit[224] => READ ERROR, bit[225] => READ OVERFLOW, bit[226] => WRITE ERROR, bit[227] => WRITE UNDERRUN and bit[228] => CALIBRATION DONE.

src/wb_sl_flash.vhd:

The module encapsulates the low level FLASH controller flash_ctrl.vhd. The integrated command register supports the BULK ERASE command, which erases the whole memory by programming all bits to '1'. In write cycles the bit values can only be changed from '1' to '0'. That means, that it is not allowed to have a write access to the same address twice without erasing the whole flash before. The read access is as simple as reading from any other WISHBONE device. Please see the SPI-FLASH data sheet for details on programming and erasing. There are two instances of this module. One is used for

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-22-	preliminary