Manuals / Company X Accessories / Musical Instruments & Equipment / Electronic Keyboard

Company X Accessories C1030-5510 manual IO pairing and etch length report, Net name, Direction

Models: C1030-5510

1 71

Download 71 pages 45.45 Kb

Page 62

IO pairing and etch length report

J3 VG-96 pin connector - Differential pairs (28 IN, 12 IN/OUT )

PIN	Net name	FPGA IO	P / N	Direction	FPGA BANK	Etch Length (mm)
A4	VG96_IO0	U2	P	IN	BANK 3	62.370
B4	VG96_IO1	U1	N	IN	BANK 3	62.368

A5	VG96_IO3	T2	P	IN	BANK 3	60.667
B5	VG96_IO4	T1	N	IN	BANK 3	60.664

C5	VG96_IO5	P4	P	IN	BANK 3	57.362
C4	VG96_IO2	P3	N	IN	BANK 3	57.362

A6	VG96_IO6	P2	P	IN	BANK 3	59.397
B6	VG96_IO7	P1	N	IN	BANK 3	59.394

A7	VG96_IO9	N2	P	IN	BANK 3	59.131
B7	VG96_IO10	N1	N	IN	BANK 3	59.129

C7	VG96_IO11	N4	P	IN	BANK 3	59.244
C6	VG96_IO8	N3	N	IN	BANK 3	59.232

A8	VG96_IO12	L2	P	IN	BANK 3	58.301
B8	VG96_IO13	L1	N	IN	BANK 3	58.299

A9	VG96_IO15	K2	P	IN	BANK 3	58.238
B9	VG96_IO16	K1	N	IN	BANK 3	58.236

C9	VG96_IO17	M3	P	IN	BANK 3	59.802
C8	VG96_IO14	M1	N	IN	BANK 3	59.761

A10	VG96_IO18	H2	P	IN	BANK 3	55.682
B10	VG96_IO19	H1	N	IN	BANK 3	55.680

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-62-	preliminary

Image 62

Company X Accessories C1030-5510 manual IO pairing and etch length report, Net name, Direction, Etch Length mm

Contents

USBS6 June 29 Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Modes of operation Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Mode Name ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller External memory Lpddr Sdram MT46H64M16LFCK-5 MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10G Fpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connector ADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designs FX-2/FPGA slave Fifo connection Introduction to example Fpga designs ISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbmafx2.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbslbram.vhd Src/xiluartmacro Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xilmcbmig Signals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slaves Design usbs6bram Example Usbs6bram.xise Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.ucf Wbslbramtb.cmd Introduction Changes to previous versions Requirements Driver installationWindows Build UDK Lets assume to use c\\udkapi Linux Drivers PCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK build ++ and .NET API API Error handlingAPI Functions in detail GetLastErrorText GetLastErrorCodeError code Kind of error Methods/Functions DeInit Device enumerationInit GetDeviceCount EnumerateDeviceType Description Static unsigned int ceDeviceGetDeviceCount GetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceUID Information gatheringGetUDKVersionString GetDeviceName GetMaxTransferSize GetBusTypeConstant Bus Close Using devicesOpen Void ceDeviceOpen ReadBlock ReadRegisterWriteRegister WriteBlock WaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromMemory SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryZ EnableBurst Void ceDeviceEnableBurstbool bEnable UDKLab Introduction Main screen UDKLab Main Screen Using UDKLab Device selection flow Fpga configuration Prepare to work with device Fpga design flashing Projects Sequence contents Add new initializing task Content panel Sequence start Register entry Register panel Data area entry Data area panel Using SPI-Flash for configuration How to store configuration data in SPI-Flash M25P16 Fpga Connection Jtag Signal Name Net name IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Direction 52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28 Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mm Table of contents Table of Contents USB PCI ++ API