ProgramFPGAFromBIN, SetTimeOut | Company X Accessories C1030-5510

Pulses the FPGA reset line for a short time. This should be used to sync the FPGA design with the host side peripherals.

ProgramFPGAFromBIN

API	Code
C++	void ceDevice::ProgramFPGAFromBIN(const char *pszFileName)

CCE_RESULT ProgramFPGAFromBIN(CE_DEVICE_HANDLE Handle, const char *pszFileName)

.NET	void ceDevice.ProgramFPGAFromBIN(string sFileName)

Program the FPGA with the Xilinx tools .bin file indicated by the filename parameter. Calls ResetFPGA() subsequently.

ProgramFPGAFromMemory

API	Code
C++	void ceDevice::ProgramFPGAFromMemory(const unsigned char *pszData, unsigned int
	uiSize)

CCE_RESULT ProgramFPGAFromMemory(CE_DEVICE_HANDLE Handle, const unsigned char *pszData, unsigned int uiSize)

.NET	void ceDevice.ProgramFPGAFromMemory(byte[] Data, uint Size)

Program FPGA with a given array created with UDKLab. This was previously done using fpgaconv.

ProgramFPGAFromMemoryZ

API	Code
C++	void ceDevice::ProgramFPGAFromMemoryZ(const unsigned char *pszData, unsigned
	int uiSize)

CCE_RESULT ProgramFPGAFromMemoryZ(CE_DEVICE_HANDLE Handle, const unsigned char *pszData, unsigned int uiSize)

.NET	void ceDevice.ProgramFPGAFromMemoryZ(byte[] Data, uint Size)

Same as ProgramFPGAFromMemory(), except the design data is compressed.

SetTimeOut

API	Code
C++	void ceDevice::SetTimeOut(unsigned int uiTimeOutMS)

CCE_RESULT SetTimeOut(CE_DEVICE_HANDLE Handle, unsigned int uiTimeOutMS)

.NET void ceDevice.SetTimeOut(uint uiTimeOutMS)

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-48-	preliminary

Image 48

Company X Accessories C1030-5510 manual ProgramFPGAFromBIN, ProgramFPGAFromMemoryZ, SetTimeOut

Contents

USBS6 June 29 Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Powering USBS6 Bus- powered USB is used as power supply input 3V@ ??? mAModes of operation Mode Configuration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5 MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10G HEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connector ADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designs FX-2/FPGA slave Fifo connection Introduction to example Fpga designs ISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/usbs6soctop.vhd Src/wbintercon.vhdSrc/wbmafx2.vhd Src/wbslbram.vhd Src/wbslmcb.vhd Src/wbsluart.vhdSrc/xiluartmacro Src/xilmcbmig Signals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slaves Design usbs6bram Example Src/usbs6bramtop.vhd Src/simtb/wbslbramtb.vhdUsbs6bram.xise Usbs6bram.ucf Wbslbramtb.cmd Introduction Changes to previous versions Driver installation WindowsRequirements Build UDK Lets assume to use c\\udkapi Linux Drivers PCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK build API Error handling API Functions in detail++ and .NET API GetLastErrorCode Error code Kind of errorGetLastErrorText Methods/Functions Device enumeration InitDeInit Enumerate DeviceType DescriptionGetDeviceCount Static unsigned int ceDeviceGetDeviceCount GetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdx Information gathering GetUDKVersionStringGetDeviceUID GetDeviceName GetBusType Constant BusGetMaxTransferSize Using devices OpenClose Void ceDeviceOpen ReadRegister WriteRegisterReadBlock WriteBlock EnableInterrupt ResetFPGAWaitForInterrupt SetTimeOut ProgramFPGAFromBINProgramFPGAFromMemory ProgramFPGAFromMemoryZ EnableBurst Void ceDeviceEnableBurstbool bEnable UDKLab Introduction Main screen UDKLab Main Screen Using UDKLab Device selection flow Fpga configuration Prepare to work with device Fpga design flashing Projects Sequence contents Add new initializing task Content panel Sequence start Register entry Register panel Data area entry Data area panel Using SPI-Flash for configuration How to store configuration data in SPI-Flash M25P16 Fpga Connection Jtag Signal Name IO pairing and etch length report J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUTNet name Direction 52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28 Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mm Table of contents Table of Contents USB PCI ++ API