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Company X Accessories C1030-5510 manual Etch Length mm B18, C19

Models: C1030-5510

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	PIN		Net name	FPGA IO	P / N	Direction	FPGA BANK	Etch Length (mm)
	B18		VG96_IO43	H5	N	IN	BANK 3	63.426

	C19		VG96_IO45	J7	P	IN	BANK 3	64.103
	C18		VG96_IO46	J6	N	IN	BANK 3	64.144

	A20		VG96_IO47	H7	P	IN	BANK 3	63.630
	B20		VG96_IO44	G6	N	IN	BANK 3	63.609

	A21		VG96_IO48	E4	P	IN	BANK 3	60.899
	B21		VG96_IO49	D3	N	IN	BANK 3	60.885

	C21		VG96_IO51	F4	P	IN	BANK 3	56.002
	C20		VG96_IO52	F3	N	IN	BANK 3	55.884

	A23		VG96_IO53	F6	P	IN	BANK 3	64.148
	B23		VG96_IO50	F5	N	IN	BANK 3	64.134

	A24		VG96_IO57	D6	P	IN / OUT	BANK 0	63.585
	B24		VG96_IO58	C6	N	IN / OUT	BANK 0	63.540

	C24		VG96_IO59	F7	P	IN / OUT	BANK 0	60.224
	C23		VG96_IO56	E6	N	IN / OUT	BANK 0	60.128

	A25		VG96_IO60	E7	P	IN / OUT	BANK 0	71.834
	B25		VG96_IO61	E8	N	IN / OUT	BANK 0	71.637

	A26		VG96_IO63	D9	P	IN / OUT	BANK 0	69.596
	B26		VG96_IO64	C9	N	IN / OUT	BANK 0	69.497

	C26		VG96_IO65	D8	P	IN / OUT	BANK 0	63.074
	C25		VG96_IO62	C8	N	IN / OUT	BANK 0	63.051

	A27		VG96_IO66	G9	P	IN / OUT	BANK 0	74.749
	B27		VG96_IO67	F9	N	IN / OUT	BANK 0	74.696

USBS6 / C1030-5510								http://www.cesys.com/
User Doc V0.3						-64-		preliminary

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Company X Accessories C1030-5510 manual Etch Length mm B18, C19

Contents

USBS6 June 29Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Powering USBS6 Bus- powered USB is used as power supply input 3V@ ??? mAModes of operation ModeJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/usbs6soctop.vhd Src/wbintercon.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbslmcb.vhd Src/wbsluart.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleSrc/usbs6bramtop.vhd Src/simtb/wbslbramtb.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsDriver installation WindowsRequirements Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Functions in detail API Error handling++ and .NET API GetLastErrorCode Error code Kind of errorGetLastErrorText Methods/FunctionsInit Device enumerationDeInit Enumerate DeviceType DescriptionGetDeviceCount Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxInformation gathering GetUDKVersionStringGetDeviceUID GetDeviceNameConstant Bus GetBusTypeGetMaxTransferSize Using devices OpenClose Void ceDeviceOpenReadRegister WriteRegisterReadBlock WriteBlockResetFPGA EnableInterruptWaitForInterrupt SetTimeOut ProgramFPGAFromBINProgramFPGAFromMemory ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name IO pairing and etch length report J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUTNet name Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API