src/wb_sl_uart.vhd:

23

src/xil_uart_macro/:

23

src/xil_mcb_mig/:

23

src/fx2_slfifo_ctrl.vhd:

23

src/sync_fifo.vhd:

25

src/sfifo_hd_a1Kx18b0K5x36.vhd:

25

src/flash_ctrl.vhd:

25

usbs6_soc.xise:

25

usbs6_soc.ucf:

25

usbs6_soc_fpga_consts.h:

25

Software Pseudo-Code Example:

25

WISHBONE transactions

25

WISHBONE signals driven by the master:

26

WISHBONE signals driven by slaves:

26

Example:

27

Design “usbs6_bram”

27

Files and modules

28

src/wishbone_pkg.vhd:

28

src/usbs6_bram_top.vhd:

28

src/wb_ma_fx2.vhd:

28

src/wb_sl_bram.vhd:

28

src/sim_tb/wb_sl_bram_tb.vhd:

28

src/fx2_slfifo_ctrl.vhd:

28

src/sync_fifo.vhd:

28

usbs6_bram.xise:

28

usbs6_bram.ucf:

28

wb_sl_bram_tb.do:

28

wb_sl_bram_tb.cmd:

29

Software

30

Introduction

30

Changes to previous versions

30

Windows

31

Requirements

31

Driver installation

31

Build UDK

31

Prerequisites

31

Solution creation and build

31

Linux

33

Requirements

33

Drivers

33

USB

33

PCI

34

Build UDK

35

 

 

 

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

-70-

preliminary

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