ADDIO16 | Company X Accessories C1030-5510 instruction

J4 IDC 2x25-Pin external expansion connector

PIN	FPGA IO	Comment	PIN	FPGA IO	Comment
25	B11	ADD_IO16	26	A11	ADD_IO17
27	B12	ADD_IO18	28	A12	ADD_IO19
29	B14	ADD_IO20	30	A14	ADD_IO21
31	B16	ADD_IO22	32	A16	ADD_IO23
33	--	GND	34	--	GND
35	C10	ADD_IO24*	36	A10	ADD_IO25*
37	D12	ADD_IO26	38	C12	ADD_IO27

39	--	GND	40	--	GND
41	C13	ADD_IO28	42	A13	ADD_IO29
43	D14	ADD_IO30	44	C14	ADD_IO31

45	C15	ADD_IO32	46	A15	ADD_IO33
47	D4	HSWAPEN**	48	--	GND
49	--	VCCO_IO	50	--	GND

* GCLK

**Enable / Disable optional pull-up resistors during configuration. Pulled HIGH via external 4,7 kOhm resistor. Leave unconnected.

!It is strongly recommended to check the appropriate data sheets of SPARTAN-6TMdevices about special functionality IO like GCLK, HSWAPEN, ...

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-16-	preliminary

Image 16

Company X Accessories C1030-5510 manual ADDIO16

Contents

USBS6 June 29 Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Powering USBS6 Bus- powered USB is used as power supply input 3V@ ??? mAModes of operation Mode Jtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5 MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10G LEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connector ADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designs FX-2/FPGA slave Fifo connection Introduction to example Fpga designs ISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/usbs6soctop.vhd Src/wbintercon.vhdSrc/wbmafx2.vhd Src/wbslbram.vhd Src/wbslmcb.vhd Src/wbsluart.vhdSrc/xiluartmacro Src/xilmcbmig Signals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slaves Design usbs6bram Example Src/usbs6bramtop.vhd Src/simtb/wbslbramtb.vhdUsbs6bram.xise Usbs6bram.ucf Wbslbramtb.cmd Introduction Changes to previous versions Driver installation WindowsRequirements Build UDK Lets assume to use c\\udkapi Linux Drivers PCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK build API Functions in detail API Error handling++ and .NET API GetLastErrorCode Error code Kind of errorGetLastErrorText Methods/Functions Init Device enumerationDeInit Enumerate DeviceType DescriptionGetDeviceCount Static unsigned int ceDeviceGetDeviceCount GetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdx Information gathering GetUDKVersionStringGetDeviceUID GetDeviceName Constant Bus GetBusTypeGetMaxTransferSize Using devices OpenClose Void ceDeviceOpen ReadRegister WriteRegisterReadBlock WriteBlock ResetFPGA EnableInterruptWaitForInterrupt SetTimeOut ProgramFPGAFromBINProgramFPGAFromMemory ProgramFPGAFromMemoryZ EnableBurst Void ceDeviceEnableBurstbool bEnable UDKLab Introduction Main screen UDKLab Main Screen Using UDKLab Device selection flow Fpga configuration Prepare to work with device Fpga design flashing Projects Sequence contents Add new initializing task Content panel Sequence start Register entry Register panel Data area entry Data area panel Using SPI-Flash for configuration How to store configuration data in SPI-Flash M25P16 Fpga Connection Jtag Signal Name IO pairing and etch length report J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUTNet name Direction 52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28 Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mm Table of contents Table of Contents USB PCI ++ API