Company X Accessories C1030-5510 manual Src/wbslmcb.vhd, Src/wbsluart.vhd, Src/xiluartmacro

programming FPGA configuration bitstream to SPI-FLASH and the other accesses QUAD- SPI-FLASH for storing nonvolatile application data.

src/wb_sl_mcb.vhd:

WISHBONE adapter for one port of Spartan-6TMbuild in multiport memory controller block (MCB).

src/wb_sl_uart.vhd:

This entity is a simple UART transceiver with 16 byte buffer for each direction connected to USB2UART interface. XilinxTM UART transceiver macros are used as physical layer. Baudrate is adjustable up to 230400 (default: 9600) by writing appropriate timer prescaling values to the status and configuration register. This register contains buffer level flags FULL and HALFFULL for each direction, too. Data format is fixed at 8-N-1. Reading from UART pipe is always non-blocking. A data present flag provided along with received bytes indicates, if current RX value is valid. Writing to UART pipe is blocking, if TX buffer gets full. So that loss of transmitted data can easily be avoided.

src/xil_uart_macro/:

This directory contains VHDL source code files of XilinxTM UART transceiver macros. Note that these source code files are copyrighted by XilinxTM and are absolutely not supported by CESYS! For details on these macros see the application note “XAPP223 - 200 MHz UART with Internal 16-Byte Buffer” provided by XilinxTM.

src/xil_mcb_mig/:

This directory contains VHDL source code files generated by XilinxTM memory interface generator tool to build the frontend for MCB. File memc1_infrastructure.vhd has been modified to fit example design requirements.

src/fx2_slfifo_ctrl.vhd:

This controller handles 512 byte aligned raw USB bulk transfers without CESYS USB transfer protocol. It checks FX-2 FIFO flags and copies data from FX-2 endpoints to internal FPGA buffers (sync_fifo.vhd) and vice versa. So the USB data link looks like any other FPGA FIFO buffer to user logic. Ports of fx2_slfifo_ctrl connected to FX-2 are labeled with prefix fx2_ and ports connected to user logic are labeled with prefix app_. Sometimes the abbreviations _h2p_ (host to peripheral) and _p2h_ (peripheral to host) are used in signal names to indicate data flow direction.

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-23-	preliminary