![](/images/new-backgrounds/1272121/27212145x1.webp)
programming FPGA configuration bitstream to
src/wb_sl_mcb.vhd:
WISHBONE adapter for one port of
src/wb_sl_uart.vhd:
This entity is a simple UART transceiver with 16 byte buffer for each direction connected to USB2UART interface. XilinxTM UART transceiver macros are used as physical layer. Baudrate is adjustable up to 230400 (default: 9600) by writing appropriate timer prescaling values to the status and configuration register. This register contains buffer level flags FULL and HALFFULL for each direction, too. Data format is fixed at
src/xil_uart_macro/:
This directory contains VHDL source code files of XilinxTM UART transceiver macros. Note that these source code files are copyrighted by XilinxTM and are absolutely not supported by CESYS! For details on these macros see the application note “XAPP223 - 200 MHz UART with Internal
src/xil_mcb_mig/:
This directory contains VHDL source code files generated by XilinxTM memory interface generator tool to build the frontend for MCB. File memc1_infrastructure.vhd has been modified to fit example design requirements.
src/fx2_slfifo_ctrl.vhd:
This controller handles 512 byte aligned raw USB bulk transfers without CESYS USB transfer protocol. It checks
USBS6 / |
| http://www.cesys.com/ |
User Doc V0.3 | preliminary |