The main screen
The following screen shows an active session with an EFM01 device. The base view is intended to work with a device, while additional functionality can be found in the tools menu.
The left part of the screen contains the device initialization details, needed to prepare the FPGA with a design (or just a reset if loaded from flash), plus optional register writes for preparation of peripheral components.
The right side contains elements for communication with the FPGA design:
•Register read and write, either by value or
•Live update of register values.
•Data areas (like RAM or Flash) can be filled from file or read out to file.
•Live view of data areas.
•More on these areas below.
Figure 11: UDKLab Main Screen
USBS6 / |
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User Doc V0.3 | preliminary |
