CIRCUIT DESCRIPTION
the VCO from the receiver and transmitter and the counters in synthesizer IC1.
A switching circuit on the output of Q10 routes the VCO signal to the receiver in the receive mode and the transmitter in the transmit mode. In the receive mode, the R5V receive supply is applied to R12 and current flows through R12, D7A, and R51. Since D7A is forward biased, it presents a low impedance path to first mixer Q2 in the receiver. D7C is then reverse biased, so there is a high impedance path to the transmitter.
The 5V receive supply is also applied to R78 and current flows through R78, D7B, and R79. This results in less reverse bias and therefore charge on D7C to permit faster switching. In the transmit mode, the 5V receive supply is no longer present, so both D7A and D7B are reverse biased. D7C is forward biased by the current path through R50 and R51.
4.2.3 VCO AND TCXO MODULATION
Both the VCO and TCXO are modulated in order to achieve the required frequency response. If only the VCO was modulated, the phase detector in IC1 would sense the frequency change and increase or decrease the VCO control voltage to counteract the change (especially at the lower audio frequencies). Conversely, if only the TCXO was modulated, the VCO frequency would not change fast enough (espe- cially at the higher audio frequencies).
However, by modulating both the VCO and
TCXO, the two phase detector inputs remain in phase and no frequency shift is sensed. This produces a rela- tively flat audio response. Potentiometer B4 in IC209 is used to balance these signals and potentiometers B1 and B3 are used to set the data and audio deviation level. IC4 is an amplifier, and R73 sets the frequency of the TCXO by adjusting the DC bias of IC4.
4.2.4 SYNTHESIZER CHIP (IC1)
Synthesizer chip IC1 contains a prescaler, A, N, and reference counters, and a phase detector. Chan- nels are selected by programming the A, N, and refer- ence counters to divide by a certain number. This programming is performed by the microprocessor via the serial data bus which consists of lines PLLSK, PLLSO, and PLLST (pins
The divide numbers are chosen so that when the VCO is operating at the correct frequency, the VCO- derived input to the phase detector is the same frequency as the
The
Both the A and N counters begin counting down from the programmed number. When the A counter reaches zero, it halts until the N counter reaches zero. Both counters then reset and the cycle repeats. The A counter is always programmed with a smaller number than the N counter. When the A counter is counting down, the control output to the prescaler causes the prescaler to divide by 129. Then when the A counter is halted, the control output changes states and the pres- caler divides by 128.
4.2.5 LOCK DETECT (Q13)
When the synthesizer is locked on frequency, the LD (Lock Detect) output of IC1 (pin 7) is a high signal. This turns lock detect transistor Q13 off and the ULOCK signal fed to the microprocessor is low. When an unlocked condition is indicated,
4.2.6 CHARGE PUMP (Q1, Q2), LOOP FILTER
The charge pump circuit consisting of Q1 and Q2 charges and discharges C4 and C5 in the loop filter to produce the VCO control voltage. Supply voltage to Q1 is provided by CPV regulator IC2 on the IF board.
Pulses which control the charge pump are output by synthesizer IC1 on pins 15 and 16. When the VCO is on the correct frequency, both phase detector outputs are in phase. Pin 15 is then high and pin 16 is low which turns both Q1 and Q2 off. Then if the VCO
November 1999 |
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