Transfer Period

The Transfer Period specifies the minimum time allowed between the leading edges of successive REQ pulses and of successive ACK pulses while using synchronous data transfers. (See ANSI SCSI-2 6.1.5.2 and ANSI SCSI-2 6.6.21.)

INTERFACE

SCSI Bus Phases The SCSI architecture includes eight distinct phases:

a)BUS FREE phase

b)ARBITRATION phase

c)SELECTION phase

d)RESELECTION phase

e)

COMMAND phase

⎫

 

f)

DATA phase

⎪

 

⎪

These phases are collectively termed

g)

STATUS phase

⎬

⎪

the information transfer phase.

h) MESSAGE phase

⎪

 

⎭

 

The SCSI bus can never be in more than one phase at any given time. In the following descriptions signals that are not mentioned shall not be asserted.

BUS FREE Phase (See ANSI SCSI-2 6.1.1 for details)

The BUS FREE phase indicates that there is no current I/O process and that the SCSI bus is available for a connection.

SCSI devices shall detect the BUS FREE phase after the SEL and

BSY signals are both false for at least a bus settle delay.

SCSI devices shall release all SCSI bus signals within a bus clear delay after the BSY and SEL signals become continuously false for a bus settle delay. If an SCSI device requires more than a bus settle delay to detect the BUS FREE phase then it shall release all SCSI bus signals within a bus clear delay minus the excess time to detect the BUS FREE phase. The total time to clear the SCSI bus shall not exceed a bus settle delay plus a bus clear delay.

M3099GX/GH OEM Manual

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