Dcache Measurement Report Metrics

L2D_REFERENCES.ALL

%of Cycles lost due to GR/load dependency stalls (lower is better)

%of Cycles lost due to GR/GR dependency stalls (lower is better)

%of Cycles lost due to FR/load and FR/FR dependency stalls (lower is better)

L1 data cache miss percentage

Percent of data references accessing L1 data cache

L2 data cache miss percentage

L1 data cache misses per 1000 instructions retired

L2 data cache misses per 1000 instructions retired

Instructions retired per L1 data cache access

Instructions retired per L2 data cache access

Number of requests made to L2D due to a data read and/or write accesses. Semaphore operations are counted as one read and one write.

Percentage of cycles lost due GR/load dependency stalls.

Percentage of cycles lost due GR/GR dependency stalls.

Percentage of cycles lost due to FR/load and FR/FR dependency stalls

Percentage of L1 data cache reads that are misses. Percentage of data references that access the L1 data cache.

Percentage of L2 data cache reads that are misses.

Number of L1 data cache misses per 1000 instruction retired.

Number of L2 data cache misses per 1000 instruction retired.

Number of instructions retired per L1 data cache access.

Number of instructions retired per L2 data cache access.

In this table, “program object” refers to any of the following:

•Thread

•Load module

•Function

•Source statement

•Instruction

Column	Description
% Total Dcache	Total cache miss latency cycles, expressed as a percent of the total cycles.
Latency Cycles	For example, in Example 5, 84.29 percent of the total cycles were expended on data cache

	misses.
Sampled Dcache	Total number of sampled data cache misses attributed to the given program object.
Misses
Dcache Latency	Number of cycles expended on data cache misses summed across samples for the given program
Cycles	object.
Avg. Dcache	Average number of cycles expended on data cache misses across samples for the given program
Laten. Cycles	object.