•Dfetch - Misses Per Second

This is the number of instruction line demand requests that miss the L3 cache per second.

•Data - Misses Per Second

This is the number of data (load and store) requests that miss the L3 cache per second. This count includes writebacks from the L2 cache that miss the L3 cache.

•Writebacks Per Second

This is the total number of L2 cache writebacks (L3 hit and miss) per second.

•Total - Misses Per Kinst

This is the total number of L3 cache misses per 1000 retired instructions, including nops and predicated off instructions. It includes instruction prefetch misses, instruction demand misses, and data misses.

•Pfetch - Misses Per Kinst

This is the number of instruction prefetch (streaming and non-streaming) requests that miss the L3 cache per 1000 retired instructions, including nops and predicated off instructions.

•Dfetch - Misses Per Kinst

This is the number of instruction line demand requests that miss the L3 cache per 1000 retired instructions, including nops and predicated off instructions.

•Data - Misses Per Kinst [narrow display only]

This is the number of data (load and store) requests that miss the L3 cache per 1000 retired instructions, including nops and predicated off instructions.

•Load - Misses Per Kinst

This is the total number of loads that miss the L3 unified cache per 1000 retired instructions, including nops and predicated off instructions.

•Store - Misses Per Kinst

This is the total number of stores that miss the L3 unified cache per 1000 retired instructions, including nops and predicated off instructions.

•L2 WB - Misses Per Kinst

This is the number of cache line writebacks that miss the L3 cache per 1000 retired instructions, including nops and predicated off instructions. Writeback misses are sent directly to memory; they do not allocate the line in the L3 cache.

•Writebacks Per Kinst

This is the total number of L2 cache writebacks (L3 hit and miss) per 1000 retired instructions, including nops and predicated off instructions.

•Instr Per Access

This is the ratio of the total number of instructions retired per L3 unified cache access. The instruction count includes nops and predicated off instructions. Accesses include all memory reference operations to include load/stores, RSE loads/stores, and instruction fetch/prefetches that miss higher levels of the cache hierarchy.

•%Miss

This is the percentage of the total number of L3 unified accesses that miss the L3 cache out of the total number of L3 accesses. The L3 is accessed by all loads/stores, RSE loads/stores, and instruction fetches/prefetches that miss higher levels of the cache hierarchy.

l3cache Event Set 241