L1I_PREFETCHES | Provides information about the number of issued L1 cache | |
|
| line prefetch requests (64 bytes/line). The reported number |
|
| includes streaming and |
|
| misses in L1 instruction cache are both included. |
L1 | Instruction Cache Read Misses | Number of L1 instruction cache read misses. |
L1 | Instruction Cache Demand Miss | Percentage of demand fetch reads that missed. |
Percentage |
| |
Total L1 Instruction Cache References | Sum of demand fetch reads and L1 cache line prefetch | |
|
| requests. |
Metrics for Integrity Servers
BACK_END_BUBBLE.ALL | Full Pipe Bubbles in Main Pipe due to all causes. |
| This is the number of cycles lost (stall cycles) due to any of |
| five possible events (FPU/L1D, RSE, EXE, branch/exception, |
| or the |
BACK_END_BUBBLE.FE | Full Pipe Bubbles in Main Pipe due to front end. |
| This is the number of cycles lost (stall cycles) due to |
| instruction cache ITLB and branch execution stalls. |
CPU_OP_CYCLES.ALL
IA64_INST_RETIRED
L1I_PREFETCHES
L1I_READS
L2I_DEMAND_READS
L2I_PREFETCHES
L2I_READS.ALL.ALL
L2I_READS.MISS.ALL
L2I_READS.MISS.DMND
%of Cycles lost due to all stalls (lower is better)
%of Cycles lost due to Front end stalls (ICACHE, ITLB and branch execution)
L1 instruction cache references
L1 instruction cache misses
L1 instruction cache miss percentage
Number of elapsed CPU operating cycles.
Number of retired
Number of issued L1 cache line prefetch requests (64 bytes/line). For more information, see L1I_PREFETCHES.
Number of demand fetch reads to the L1 instruction cache
Number of instruction requests to L2 instruction cache due to L1 instruction cache demand fetch misses. This includes the number of demand fetches that miss both the L1 instruction cache and the ISB, regardless of whether they hit or miss in the RAB.
Number of prefetch requests issued to the L2 instruction cache. This includes streaming and
Number of cacheable code reads handled by the L2 instruction cache.
Number of demand fetch and prefetch misses in cacheable code reads handled by the L2 instruction cache. This only includes the primary misses.
Number of demand fetch misses in cacheable code reads handled by the L2 instruction cache. This includes the primary misses.
Percentage of cycles lost due to all stalls.
Percentage of cycles lost due to instruction cache, instruction translation lookaside buffer, and branch execution stalls.
Number of L1 instruction cache references.
Number of L1 instruction cache prefetch and demand fetch misses.
Percentage of L1 instruction demand fetch and prefetch that are misses.
icache Measurement Report Description 205