•I1TLB Misses Per Kinst
This is the number of level 1 ITLB misses per 1000 retired instructions. The retired instruction count includes predicated off and nop instructions. Level 1 ITLB misses are normally satisfied by the level 2 ITLB.
•I2TLB Misses Per Kinst
This is the number of Level 2 ITLB misses per 1000 retired instructions. The retired instruction count includes predicated off and nop instructions. Misses at this level of the ITLB are initially attempted to be satisfied by the HPW. If the walker is unsuccessful, a trap will be taken to the software TLB manager to resolve the requisite translation.
•D1TLB Misses Per Kinst
This is the number of level 1 DTLB misses per 1000 retired instructions. The retired instruction count includes predicated off and nop instructions. Level 0 DTLB misses are normally satisfied by the Level 2 ITLB
•D2TLB Misses Per Kinst
This is the number of level 2 DTLB misses per 1000 retired instructions. The retired instruction count includes predicated off and nop instructions. Misses at this level of the ITLB are initially attempted to be satisfied by the HPW. If the walker is unsuccessful, a trap will be taken to the software TLB manager to resolve the requisite translation.
•%ITLB H/W Update
This is the percentage of level 2 ITLB misses out of ITLB hardware inserts. This would normally be a metric of the effectiveness of the HPW. However, this might not always be the case. The problem is that it is possible for ITLB misses to be counted for speculative accesses that are later rescinded. Thus, the trap might not occur, but it is counted as though it did occur. Under some conditions, this can cause the metric to suggest very low HPW effectiveness.
This problem generally only occurs when there is a loop that has a statically mispredicted branch. This can lead to accesses to code that is never executed and thus never in the cache, but is continually being accessed by the mispredicted branch. This results in an ITLB miss, which is then dismissed before the trap is actually taken.
•%DTLB H/W Update
This is the percentage of level 2 ITLB misses out of ITLB hardware inserts. This is a metric of the effectiveness of the HPW.
252 Event Set Descriptions for CPU Metrics 