measurement. You can use
•Limit measurement to a specific privilege level:
•Include idle:
•Exclude the interruption state:
•Only measure the interruption state:
The event per kinst (event per 1000 instructions) metrics are computed using all instructions retired. This includes nops, predicated off instructions, failed speculation and instructions and associated recovery code as well as the architecturally visible instruction. You can eliminate idle loops effects by using the
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take into account any
The metrics are:
•Total - Misses Per Sec
This is the number of demand instruction cache line accesses and instruction prefetch cache lines accesses that miss the L1 instruction cache and ISB per second.
•Dfetch - Misses Per Sec
This is the number of demand instruction cache line accesses that miss both the L1 instruction cache and the ISB.
•Pfetch - Misses Per Sec
This is the number of streaming and
•Total - Misses Per Kinst
This is the number of demand instruction cache line accesses that and instruction prefetch cache lines accesses that miss the L1 instruction cache and ISB per 1000 instructions retired.
•Dfectch - Misses Per Kinst
This is the number of demand instruction cache line access that miss the L1 instruction cache and ISB per 1000 instructions retired.
•Pfetch - Misses Per Kinst
This is the number of streaming and
•Ifills Per Kinst
This the number of (64 byte) lines per 1000 instruction retired that are moved from the ISB to the L1I cache. For the Itanium 2 family of processors (McKinley, Madison, and Deerfield), this should be approximately equal to the number of ISB Lines per 1000 instructions retired.
•ISB Lines Per Kinst
This is the number of cache line chunks (64 bytes) that were delivered from the L1 cache and beyond to the the ISB per 1000 instructions retired. For the Itanium 2 family of processors
234 Event Set Descriptions for CPU Metrics