BE_LOST_BW_DUE_TO_FE.IMISS

BE_LOST_BW_DUE_TO_FE.TLBMISS

CPU_OP_CYCLES.ALL

IA64_INST_RETIRED

ITLB_MISSES_FETCH.L1ITLB

ITLB_MISSES_FETCH.L2ITLB

L1ITLB_INSERTS_HPW

L1I_READS

%of Cycles lost due to all stalls (lower is better)

%of Cycles lost due to Front end stalls (ICACHE, ITLB, and branch execution)

%of Cycles lost due to instruction TLB stalls

%of Cycles lost due to instruction cache stalls

%of Cycles lost due to instruction access stalls (ICACHE and ITLB)

%of Cycles lost due to branch execution

Total L1 instruction TLB references

L1 instruction TLB miss percentage

L2 instruction TLB misses

Percentage of L2 ITLB misses covered by the HPW

L1 ITLB miss per 1000 instructions retired

L2 ITLB miss per 1000 instructions retired

Number of invalid bundles at the exit from Instruction Buffer due to instruction cache miss stalls (only if the back end is not stalled for other reasons).

Number of invalid bundles at the exit from Instruction Buffer due to instruction TLB miss stalls (only if the back end is not stalled for other reasons).

Number of elapsed CPU operating cycles.

Number of retired IA-64 instructions. The count includes predicated on and predicated off instructions and nops, but excludes hardware-inserted RSE operations.

Number of L1 ITLB misses for demand fetch. Number of L2 ITLB misses for demand fetch.

Number of instruction TLB inserts done by the hardware page walker (HPW).

The number of data memory read references issued into the memory pipeline that are serviced by L1D (only integer loads), RSE loads, L1-hinted loads (L1D returns data if it hits in L1D but does not do a fill), and check loads (ld.c). Non-cacheable reads, VHPT loads, semaphores, floating-point loads, and lfetch instructions are not counted here because L1D does not handle these. The count includes wrong path operations but excludes predicated off operations.

Percentage of cycles lost due to all stalls.

Pecentage of cycles lost due to ICACHE, ITLB and branch execution stalls.

Percentage of cycles lost due to instruction TLB miss stalls.

Perdcentage of cycles lost due to instruction cache miss stalls.

Perdcentage of cycles lost due to instruction cache miss and instruction TLB miss stalls.

Percentage of cycles lost due to branch execution (branch re-steer).

Number of L1 instruction TLB references.

Percentage of L1 instuction TLB accesses that missed. Number of L2 instruction TLB misses.

Percentage of L2 ITLB misses that were serviced by the hardware page walker (HPW).

Number of L1 ITLB misses per 1000 instructions retired.

Number of L2 ITLB misses per 1000 instructions retired.

itlb Measurement Report Metrics

See Table 28 (page 210).

In this table, “program object” refers to any of the following:

•Thread

•Load module

itlb Measurement Report Description 209