DTLB_INSERTS_HPW

IA64_INST_RETIRED

L1DTLB_TRANSFER

L1D_READS

L2DTLB_MISSES

%of Cycles lost due to all stalls (lower is better)

%of Cycles lost due to GR/load dependency stalls (lower is better)

%of Cycles lost due to GR/GR dependency stalls (lower is better)

%of Cycles lost due to FR/load and FR/FR dependency stalls (lower is better)

Total L1 data TLB references

L1 data TLB for L1D miss percentage

L2 data TLB misses

L2 data TLB miss percentage

Percentage of L2 DTLB misses covered by the HPW

Percentage of data references covered by L1 and L2 DTLB

Percentage of data references covered by the HPW:

Percentage of data references covered by software trap

L1 DTLB miss per 1000 instructions retired

L2 DTLB miss per 1000 instructions retired

excludes predicated off operations. This event does not include VHPT memory references.

Number of virtual hash page table entries inserted into the DTLB by the hardware page walker (HPW).

Number of retired IA-64 instructions. The count includes predicated on and predicated off instructions and nops, but excludes hardware-inserted RSE operations.

Number of times an L1 DTLB miss hits in the L2 DTLB for an access counted in L1D_READS.

The number of data memory read references issued into memory pipeline that are serviced by the L1 data cache (only integer loads), RSE loads, L1-hinted loads (the L1 data cache returns data if it hits in the L1 data cache but does not do a fill), and check loads (ld.c). Non-cacheable reads, VHPT loads, semaphores, floating-point loads, and lfetch instructions are not counted here because the L1 data cache does not handle these. The count includes wrong path operations but excludes predicated off operations.

The number of L2 DTLB misses (which is the same as references to HPW, DT LB_HIT=0) for demand requests.

Percentage of cycles lost due to all stalls.

Percentage of cycles lost due GR/load dependency stalls.

Percentage of cycles lost due GR/GR dependency stalls.

Percentage of cycles lost due to FR/load and FR/FR dependency stalls

Number of L1 data TLB references.

Percentage of L1 DTLB accesses that are misses. Number of L2 data TLB misses.

Percentage of L2 DTLB accesses that are misses.

Percentage of L2 DTLB misses that were serviced by the hardware page walker (HPW).

Percentage of data references that was satisfied in L1 DTLB or L2 DTLB.

Percentage of data references that were satisfied by the hardware page walker (HPW).

Percentage of data references that were serviced by the software trap handler for the TLB misses fault.

Number of L1 DTLB misses per 1000 instructions retired.

Number of L2 DTLB misses per 1000 instructions retired.

dtlb Measurement Report Metrics

See Table 22 (page 196).

In this table, “program object” refers to any of the following:

•Thread

•Load module

dtlb Measurement Report Description 195