•Instr Per Access

This is the ratio of the total number of instructions retired per L2 instruction cache access, including nops and predicated off instructions. The L2 instruction cache accesses include demand fetches and prefetches that miss the L1 instruction cache.

•%Miss - Total

This is the percentage of all the L2 instruction cache misses out of the total number of L2 instruction cache accesses. Accesses include instruction fetches/prefetches that miss the L1 instruction.

•%Miss - Pfetch

This is the percentage of all the L2 instruction prefetch misses out of the total number of L2 instruction prefetch accesses.

•%Miss - Dfetch

This is the percentage of all the L2 instruction demand fetch misses out of the total number of L2 instruction demand fetch accesses.

l3cache Event Set

The l3cache event set provides miss rate information for the L3 unified cache, including miss information for instruction prefetch requests, instruction demand requests, integer loads and stores as well as L2 cache writebacks that might either hit or miss the L3 cache.

If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the measurement. You can use command-line options to limit the scope of the measurement. Specifically, you can:

•Limit measurement to a specific privilege level: -m event_set[:alluserkernel]

•Include idle: --exclude-idle False

•Exclude the interruption state: --measure-on-interrupts off

•Only measure the interruption state: --measure-on-interrupts only

The event per kinst (event per 1000 instructions) metrics are computed using all instructions retired. This includes nops, predicated off instructions, failed speculation and instructions and associated recovery code as well as the architecturally visible instruction. You can eliminate idle loops effects by using the command-line option --exclude-idle True (which is the default). The effects of failed speculative operations and TLB misses cannot be directly eliminated, but you can get an estimate of the impact of events from the cspec, dspec, and tlb event sets. You can use the cpi event set to obtain the fraction of all instructions retired that have an architecturally visible result, except for predicated off branches, which are counted as useful instructions (non-taken branch) by the Itanium 2 PMU.

Metrics Available from this Measurement

The following metrics are available from this event set. These descriptions do not take into account any command-line options you might use.

The metrics are:

•Total - Misses Per Second

This is the total number of L3 cache misses per second. It includes all instruction prefetch misses, instruction demand misses, and data misses.

•Pfetch - Misses Per Second

This is the number of instruction line prefetch requests (streaming and non streaming) that miss the L3 cache per second.

240 Event Set Descriptions for CPU Metrics