NOTE: In
If this problem occurs, the result can be a large number of samples reported as “unattributed” in
See
Specifies the bits to program the PMU's opcode matching registers. Forces PMU event monitoring to be constrained based on Itanium processor encoding (opcode) of an instruction.
OPCODE_MATCH_CHANNEL | is 0 or 1. 0 corresponds to PMC 8 on Itanium2, and PMC 32 and |
| 33 on Integrity servers |
| |
| PMC 34 and 35 on Integrity servers |
| Itanium 9300 |
MFIB | is a combination of characters 'm', 'i', 'f' and 'b'. It is used to |
| specify whether to match |
OPCODE_MATCH | is the opcode bit value against which the instruction encoding is |
| to be matched. On Integrity servers |
| Itanium 9300 |
| less. On Itanium2, it is an integer of |
OPCODE_MASK | is the mask bit value to apply to the instruction encoding before |
| matching the OPCODE_MATCH bits. On Integrity servers |
| Itanium 2 and Itanium 9300 |
| of |
| or less. |
PROC_FLAGS | is a |
| "ibrp1", "ibrp2" or "ibrp3". The values "inv" and "ign" set the |
| "inv" and "ig_ad" bits of the opcode match register. These bits |
| are cleared by default. The values "ibrp0", "ibrp1", "ibrp2" and |
| "ibrp3" will clear the corresponding bits in the opcode match |
| configuration register. These bits are set by default.. |
See
See
66 HP Caliper Options