HP UX Caliper Software manual Set p, Glossary

data speculation	The execution of a memory load prior to a store which preceded it and which might potentially
	alias with it. Data speculation loads are also referred to as advance loads. See “dspec Event
	Set” (p. 228).
databases	The directory where output databases are created for each data collection run of HP Caliper,
directory	unless you use the -doption. By default, the databases directory is a directory called
	.hp_caliper_databases in your current directory. You can override this by setting the
	CALIPER_DATABASES environment variable to point to another location.
dataset	A set of performance data collected by a single HP Caliper measurement run. Examples of datasets
	are: Run Summary, Memory Usage, Process Tree, Histogram, Call Graph, and so forth. Each HP
	Caliper measurement run produces several datasets.
dcache	A measurement, provided by the dcache measurement configuration file, that measures and
measurement	reports data cache misses as well as other data cache metrics.
dcache_miss	The non-preferred name for the dcache measurement. This name was used in releases prior to
measurement	Release 3.9.
disassembly listing	A source listing in HP Caliper reports with disassembly code for the top performance bottlenecks.
	Disassembly listings show instruction templates and symbolic representations of branch targets.
dtlb measurement	A measurement, provided by the dtlb measurement configuration file, that measures and reports
	data translation lookaside buffer (TLB) misses.
dtlb_miss	The non-preferred name for the dtlb measurement. This name was used in releases prior to
measurement	Release 3.9.
ecount	A measurement, provided by the ecount measurement configuration file, that measures and
measurement	reports total CPU event counts.
event address	The component of the Integrity servers processor that records the instruction and data addresses
register (EAR)	of data cache misses for loads, the instruction and data addresses of data TLB misses, and the
	instruction addresses of instruction TLB and cache misses.
	See also data event address register (D-EAR), instruction event address register (I-EAR).
event set	A predefined collection of CPU events to be sampled with the cpu measurement. See “Performing
	CPU Metrics Analysis ” (p. 151).
execution trace	See branch trace buffer (BTB)/execution trace buffer (ETB).
buffer (ETB)
fcount	A measurement, provided by the fcount measurement configuration file, that measures and
measurement	reports function counts in a program.
fcover	A measurement, provided by the fcover measurement configuration file, that measures and
measurement	reports functions used by a program.
fprof measurement	A measurement, provided by the fprof measurement configuration file, that measures and
	reports sampled instruction addresses.
front side bus (FSB)	A bus that connects the central processing unit with main memory. Also known as processor bus,
	memory bus, or system bus.
func_count	The non-preferred name for the fcount measurement. This name was used in releases prior to
measurement	Release 3.9.
func_cover	The non-preferred name for the fcover measurement. This name was used in releases prior to
measurement	Release 3.9.
functional unit	A subsystem of a central processing unit.
global	A measurement that gives you total run metrics of your program. See “Global Measurement”
measurement	(p. 26).
gprof fallacy	The possibly misleading results that are produced by gprof-like reports regarding the amount
	of time spent in a function. See “gprof Fallacy and Possibly Misleading Results” (p. 131).
hardware page	In the Integrity servers processor family, the part of the processor that performs page lookups
walker (HPW)	from the virtual hash page table (VHPT) and seeks opportunities to insert translations into the
	translation lookaside buffers (TLBs). TLB misses are handled by the HPW first. If the HPW fails to
	find the required mapping information, the operating system than handles the TLB misses.

254 Glossary