HP UX Caliper Software manual Cpubus Event Set

misses and excessive speculation control and data speculation fails. An estimate of any bias introduced by these events can be developed from information available in the tlb, cspec, and dspec event sets.

cpubus Event Set

Available only on Itanium 2 and dual-core Itanium 2 systems.

The cpubus event set provides information on the demand that a specific CPU presents to the central electronics complex (CEC), the chip set surrounding the CPU, and the demand the CPU experiences due to the CEC traffic initiated by other CPUs or I/O components in the system.

If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the measurement. You can use command-line options to limit the scope of the measurement. Specifically, you can:

•Limit measurement to a specific privilege level: -m event_set[:alluserkernel]

•Include idle: --exclude-idle False

•Exclude the interruption state: --measure-on-interrupts off

•Only measure the interruption state: --measure-on-interrupts only

Metrics Available from this Measurement

The following metrics are available from this event set. These descriptions do not take into account any command-line options you might use.

The metrics are all per-second metrics. The metrics are:

•Imiss

This is the instruction demand fetch misses per second produced by the local processor. This does not include instruction prefetch requests that miss the L3 cache.

•Dmiss

This is the data (load and store) misses per second produced by the local processor.

•C2C

This is the number of implicit writebacks (C2C) per second that occur as a result of data cache misses produced by the local processor referenced data that is in the modified state in a remote cache.

•WB

This is the number of writebacks per second that occur in the local processors cache in response to data cache misses replacing modified lines. It does not include implicit writebacks that are initiated in response to remote coherence requests.

•Ccast Out

Counts the number of writeback memory write transactions (BWL writes due to M-state line writebacks and coalesced writes) per second. Only counts zero-byte transactions with the writeback attribute (clean castouts) from the local CPU.

•Flush

This is the number of flush cache (fc) operations executed per second by the local processor.

•Prtl

This is the total number of partial (less than 128 byte) reads (BRP) or writes (BWP) initiated by the local processor per second. Partial transactions are normally due to reading/writing memory-mapped I/O control registers, semaphore operations, clean castouts (if monitoring a system with directory-based cache coherency), and sending interprocessor interrupts.

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