HP UX Caliper Software Itlb Measurement Report Description, Itlb Metrics Summed for Entire Run

itlb Measurement Report Description

With the itlb measurement, produced by the itlb measurement configuration file, HP Caliper measures and reports two levels of information:

•Exact counts of instruction translation lookaside buffer (TLB) metrics summed across the entire run of an application

•Sampled instruction TLB metrics that are associated with particular locations in the application The report shows masured data by thread, load module, function, statement, and cache line.

Command-line options allow you to control the amount of data reported, how the data is sorted, and the number of statements and instructions reported for each sampled program location.

Example Command Line for Text Report

$ caliper itlb -o reports/itlbm.txt ./matmul

Example Command Line for CSV Report

$ caliper itlb --csv csvout ./matmul

itlb Metrics Summed for Entire Run

This section describes the metrics summed over the entire run of your application under HP Caliper.

Metrics for Integrity Servers Itanium 2 Systems

L1I_READS	The number of data memory read references issued into the
	memory pipeline that are serviced by L1D (only integer
	loads), RSE loads, L1-hinted loads (L1D returns data if it hits
	in L1D but does not do a fill), and check loads (ld.c).
	Non-cacheable reads, VHPT loads, semaphores,
	floating-point loads, and lfetch instructions are not counted
	here because L1D does not handle these. The count includes
	wrong path operations but excludes predicated off
	operations.
ITLB_MISSES_FETCH.L1ITLB	Number of L1 instruction TLB misses for demand fetch.
	Misses are counted even if the L1 instruction TLB is not
	updated for an access (non-cacheable/nat page/not present
	page/faulting/some flushed), it will be counted here.
ITLB_MISSES_FETCH.L2ITLB	Number of L1 instruction TLB misses that also missed in the
	L2 instruction TLB.
Total L1 Instruction TLB References	Total number of L1 instruction TLB references.
L1 Instruction TLB Miss Ratio	Ratio of L1 instruction TLB misses to Total L1 instruction TLB
	references.

Metrics for Integrity Servers Dual-Core Itanium 2 and Itanium 9300 Quad-Core Processor Systems

BACK_END_BUBBLE.ALL	Number of cycles when the back end of the pipeline was
	stalled. This is the number of cycles lost (stall cycles) due to
	any of five possible events (FPU/L1D, RSE, EXE,
	branch/exception, or the front end).
BACK_END_BUBBLE.FE	Full Pipe Bubbles in Main Pipe due to front end. This is the
	number of cycles lost (stall cycles) due to ICACHE ITLB and
	branch execution stalls.
BE_LOST_BW_DUE_TO_FE.ALL	Number of invalid bundles at the exit from Instruction Buffer
	only if the back end is not stalled for other reasons.

208 Descriptions of Measurement Reports