the HPW will terminate and initiate a trap to software to provide the required TLB entry. This component counts the stall component only due to the HPW providing the required TLB entry. Time spent in the software trap handler is not counted in this component.
•Dcache
This counts the number of cycles stalled due to data cache misses at any level of the cache hierarchy (L1, L2, L3). Due to event limitations, it is not possible to distinguish between
•RSE Active
This counts the number of cycles that the pipeline is stalled due to the Register Save Engine spilling/filling registers to/from memory.
sysbus Event Set
Available only on Itanium 2 and
The sysbus event set provides data on system bus utilization and its breakdown into:
•Transaction originator (all, local cpu, io)
•Transaction type (brl, bril, bil, bwl, partial)
If you use this option, you must use the
If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the measurement. You can use
•Limit measurement to a specific privilege level:
•Include idle:
•Exclude the interruption state:
•Only measure the interruption state:
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take into account any
The metrics are:
•Avg Lat
Average memory read latency provides a measure of the number of CPU cycles required to service a memory cache line read from the perspective of the bus request queue (BRQ). The time measured includes the arbitration cycles, address cycles, memory controller/memory cycles, and data return cycles.
The reported average latency will be incorrect on Itanium 2 steppings earlier than B2.
sysbus Event Set 247