Metrics Available from this Measurement

The following metrics are available from this event set. These descriptions do not take into account any command-line options you might use.

The metrics are:

•Cycles

This is the total number of CPU cycles collected during the measurement sample period.

•IA64 Instr

This is the total number of IA64 instructions retired during the measurement sample period. Irrespective of qualification, the count includes predicated off instructions, nops, and failed speculative instructions. Depending on qualification level, the count may also include system idle loop instruction, speculative recovery code, all trap code, and instructions executed during the handling of external interrupts. The default mode would count all instructions irrespective of execution state.

•Nops

This is the total number of nop instructions retired during the measurement sample period. In the default mode, this count will include executed nops irrespective of execution state.

•Pred-Off

This is the approximate total number of predicated off instructions retired during the measurement sample period. The reason it is not the precise number of predicated off instruction is due to an Itanium 2 PMU quirk: It counts predicated off branches as executed branches that were not taken. In effect, the Itanium 2 implementation considers all predicated off branches to be useful instructions. You can use a command-line argument to qualify measurement scope to a specific CPU execution state. The default mode count includes all predicated off instructions, subject to the Itanium 2 semantics, irrespective of CPU execution state.

•%Useful

This gives an estimate of the percentage of instructions that have an architecturally visible result. It is only an estimate, because predicated off branches are considered useful as a result of the semantics that the Itanium 2 ascribes to predicated off instructions.

•%Nops

This is the percentage of instructions that were observed during the sample period that were NOPS.

•%Pred

This is an estimate of the percentage of instructions that are predicated off. It is only an estimate, because Itanium 2 semantics consider predicated off branches to be useful instructions, (that is, an untaken branch).

•Avg Mhz (present only in Itanium 9300 quad-core processor systems)

This is the average quad-core processor clock frequency observed during the measurement period.

•CPI

There are two variants of this metric: raw and effective. The raw CPI is computed using all instructions retired. The effective CPI metric excludes nops and predicated off instructions, subject to the Itanium 2's predicated off semantics. The effective metric is primarily useful when attempting to do cross architecture comparisons.

•MIPS

There are two variants of this metric: raw and effective. The raw MIPS is computed using the raw CPI. The effective MIPS is more useful when attempting to develop a relationship between throughput and execution rate. However, care must be taken to ensure that there is not excess idle (or the -Iexclude idle flag is used). Other complications can arise from excessive TLB

224 Event Set Descriptions for CPU Metrics