BWL

Bus Writeback Line is used when a dirty cache line is replaced as a consequence of servicing a BRL or BRIL bus transaction.

BRC

This is the number of current memory read transactions on the bus.

BIL

Bus Invalidate Line is used to cause lines to be flushed from the cache. Since Itanium 2 does not implement the BIL optimization, this can only be generated by the fc (flush cache) instruction. This is a zero-byte memory read transaction, although an implicit writeback will occur if the BIL hits a modified line.

Ccast Out

These zero-byte write transactions would normally only occur in systems that use directory-based cache coherence. The purpose of this transaction is to inform the coherency directory that a clean cache was evicted from the CPU's cache (that is, it is no longer an owner of the cache line). Snoopy-based cache coherency systems do not require this notification, because all caches are automatically interrogated on all memory cache line reads/writes.

PRTL

This is the number of partial (less than 128 byte) reads (BRP) or writes (BWP) per second. Partial transactions are normally due to reading/writing memory-mapped I/O control registers, semaphore operations, clean castouts (if monitoring a system with directory-based cache coherency), and sending interprocessor interrupts.

threadswitch Event Set

Available only on dual-core Itanium 2 systems.

The threadswitch event set provides data about the impact of HyperThreading on the measured process. It provides a full statistical breakdown of thread switch activity.

HyperThreading (formally called Hyper-Threading Technology) provides the ability for a processor to create an additional logical processor that might allow additional efficiencies of processing. For example, a dual-core Itanium 2 processor with HyperThreading active provides four logical processors, two on each core. An Itanium 9300 quad-core processor with HyperThreading active provides eight logical processors. This allows the operating system to schedule two threads or processes simultaneously. The effect that HyperThreading has on performance depends heavily on the application. HyperThreading can increase the overall throughput of an application, but individual processes are usually slowed down by it.

If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the measurement. You can use command-line options to limit the scope of the measurement. Specifically, you can:

Limit measurement to a specific privilege level: -m event_set[:alluserkernel]

Include idle: --exclude-idle False

Exclude the interruption state: --measure-on-interrupts off

Only measure the interruption state: --measure-on-interrupts only

Metrics Available from this Measurement

The following metrics are available from this event set. These descriptions do not take into account any command-line options you might use.

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HP UX Caliper Software manual Threadswitch Event Set, Bwl, Brc, Bil, Prtl