Figure 5-36: Determination of processor mode in LPAR

Just as certain memory areas are protected from access in user mode, some memory areas, such as hardware page tables, are accessible only in hypervisor mode. The PowerPC and POWER architecture provides only one system call instruction. This system call instruction, sc, is used to perform system calls from the user space intended for the SLES kernel, as well as hypervisor calls from the kernel space intended for the hypervisor. Hypervisor calls can only be made from the supervisor state. This access restriction to hypervisor calls is implemented with general purpose registers GPR0 and GPR3, as follows.

Figure 5-37: Transition to supervisor or hypervisor state

Actual physical memory is shared between logical partitions. Therefore, one more level of translation apart from the four levels described by System p section 5.5.2.2 is required to go from the effective address to the

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IBM 10 SP1 EAL4 manual Determination of processor mode in Lpar