Page address translation begins with a check to see if the effective segment ID, corresponding to the effective address, exists in the Segment Lookaside Buffer (SLB). The SLB provides a mapping between Effective Segment Ids (ESIDs) and Virtual Segment Ids (VSIDs). If the SLB search fails, a segment fault occurs. This is an Instruction Segment exception or a data segment exception, depending on whether the effective address is for an instruction fetch or for a data access. The Segment Table Entry (STE) is then located with the Address Space Register and the segment table.
(PP)bits from the Page Table Entry, to determine whether supervisor and user programs can access a page. Page access permissions are granular to no access, read only access, and
Key = (Kp & MSR[PR]) (Ks & ~MSR[PR])
That is, in supervisor mode, use the Ks bit from the STE and ignore the Kp bit. In user mode, use the Kp bit and ignore the Ks bit.
The following diagram schematically describes the Page Address Translation mechanism and the access control performed by it.
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