Figure 5-45: Block Address Translation entry
•Vs: Supervisor mode valid bit. Used with MSR[PR] to restrict translation for some block addresses.
•Vp: User mode valid bit. Used with MSR[PR] to restrict translation for some block addresses.
•PP: Protection bits for block.
5.5.2.3.5Address translation mechanisms
The following simplified flowchart describes the process of selecting an address translation mechanism based on the MSR settings for instruction (IR) or data (DR) access. For performance measurement, the processor concurrently starts both Block Address Translation (BAT) and Segment Address Translation. BAT takes precedence; therefore, if BAT is successful, Segment Address Translation result is not used.
Figure 5-46: Address translation method selection
The following sections describe the three address translation mechanisms, and the access controls they perform.
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