IBM SG24-4576-00 manual Performance Impact, Memory Options and Speed, Bus Architectures

1.4.5 Performance Impact

As previously discussed, systems which employ ECC memory have slightly longer memory access times depending on where the checking is done. It should be stressed that this affects only the access time of external system memory, not L1 or L2 caches. Table 1 shows the performance impacts as a percentage of system memory access times of the different ECC memory solutions.

Again, these numbers represent only the impact to accessing external memory. They do not represent the impact to overall system performance which is harder to measure but will be substantially less.

Table 1.	ECC Memory Performances
	S I M M	Memory	Impact to	Systems where
		Controller	Access Time	implemented
ECC	X	X	3 %	PC Servers 500 and 720
ECC-P		X	14%	No more (Mod 85)
EOS	X		None	Option for PC Servers
				300, 320
				Standard for PC Servers
				520

1.4.6 Memory Options and Speed

The following memory options are available from IBM:

∙4MB, 8MB, 16MB, 32MB 70 ns Standard (Parity) Memory SIMMs

∙4MB, 8MB, 16MB, 32MB 70 ns ECC Memory SIMMs

∙4MB, 8MB, 16MB, 32MB 60 ns ECC Memory SIMMs

∙4MB, 8MB, 16MB, 32MB 70 ns EOS Memory SIMMs

Table 2 shows the options used by each PC server.

Table 2. Summary of Memory Implementations

PS/2 Model	70 ns	70 ns	70 ns	60 ns	70 ns
	Standard	ECC-P	ECC	ECC	EOS
PC Server	X				OPT
300/310/320
PC Server 500			X
PC Server 520					X
PC Server 720				X

1.5 Bus Architectures

There are a number of bus architectures implemented in IBM PC servers:

∙

∙

∙

∙

ISA

EISA

MCA

PCI

12NetWare Integration Guide