IBM SG24-4576-00 manual Multiprocessing, Memory

1.2 Multiprocessing

Multiprocessing uses two or more processors in a system to increase throughput. Multiprocessing yields high performance for CPU intensive applications such as database and client/server applications.

There are two types of multiprocessing:

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Asymmetric Multiprocessing Symmetric Multiprocessing

Asymmetric Multiprocessing: In asymmetric multiprocessing the program tasks (or threads) are strictly divided by type between processors and each processor has its own memory address space. These features make asymmetric multiprocessing difficult to implement.

Symmetric Multiprocessing (SMP): Symmetric multiprocessing means that any processor has access to all system resources including memory and I/O devices. Threads are divided evenly between processors regardless of type. A process is never forced to execute on a particular processor.

Symmetric multiprocessing is easier to implement in network operating systems (NOSs) and is the method used most often in operating systems that support multiprocessing. It is the technology currently used by OS/2 SMP, Banyan Vines, SCO UNIX, Windows NT, and UnixWare 2.0.

The IBM PC Server 320, 520, and 720 support SMP. The PC Server 320 and 520 support two-way SMP via an additional Pentium processor in a socket on the planar board. The 720 supports two-to-six way SMP via additional processor complexes.

1.3 Memory

The system design of PC servers (in fact all microprocessor-based systems) is centered around the basic memory access operation. System designers must always tune this operation to be as fast as possible in order to achieve the highest possible performance.

Processor architectures always allow a certain number of clock cycles in order to read or write information to system memory. If the system design allows this to be completed in the given number of clock cycles, then this is called a zero wait state design.

If for some reason the operation does not complete in the given number of clocks, the processor must wait by inserting extra states into the basic operation. These are called wait states and are always an integer multiple of clock cycles. The challenge is that as each new generation of processors is clocked faster, it becomes more expensive to incorporate memory devices that have access times allowing zero wait designs. For example, state of the art Dynamic Random Access Memory, or DRAM, has a typical access time of about 60 nanoseconds (ns). A 60 ns DRAM is not fast enough to permit a zero wait state design with a Pentium class processor. Static RAM, or SRAM, has an access time of less than 10 ns. A 10 ns SRAM design would allow for zero waits at current processor speeds but would be prohibitively expensive to implement as main memory. A basic trade-off that all system designers must face is simply that as the access time goes down, the price goes up.

Chapter 1. IBM PC Server Technologies 3