Instruction Set
Table
Source | Operation | |
Form | ||
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ROR opr |
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RORA |
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RORX | Rotate Byte Right through Carry Bit | |
ROR opr,X |
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ROR ,X |
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RSP | Reset Stack Pointer | |
RTI | Return from Interrupt | |
RTS | Return from Subroutine | |
SBC #opr |
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SBC opr |
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SBC opr | Subtract Memory Byte and Carry Bit from | |
SBC opr,X | Accumulator | |
SBC opr,X |
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SBC ,X |
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SEC | Set Carry Bit | |
SEI | Set Interrupt Mask | |
STA opr |
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STA opr |
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STA opr,X | Store Accumulator in Memory | |
STA opr,X |
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STA ,X |
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STOP | Stop Oscillator and Enable IRQ Pin | |
STX opr |
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STX opr |
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STX opr,X | Store Index Register In Memory | |
STX opr,X |
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STX ,X |
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SUB #opr |
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SUB opr |
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SUB opr | Subtract Memory Byte from Accumulator | |
SUB opr,X | ||
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SUB opr,X |
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SUB ,X |
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SWI | Software Interrupt | |
TAX | Transfer Accumulator to Index Register | |
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Description
C
b7b0
SP ← $00FF
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL)
SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL)
A ← (A) – (M) – (C)
C ← 1
I ← 1
M ← (A)
M ← (X)
A ← (A) – (M)
PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte
X ← (A)
Effect on | Address Mode | Opcode | Operand | Cycles | |||||
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H | I | N | Z | C |
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| DIR | 36 | dd | 5 | |
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| INH | 46 |
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— | — | ↕ | ↕ | ↕ | INH | 56 |
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| IX1 | 66 | ff | 6 | |
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| IX | 76 |
| 5 | |
— | — | — | — | — | INH | 9C |
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↕ | ↕ | ↕ | ↕ | ↕ | INH | 80 |
| 9 | |
— | — | — | — | — | INH | 81 |
| 6 | |
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| IMM | A2 | ii | 2 | |
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| DIR | B2 | dd | 3 | |
— | — | ↕ | ↕ | ↕ | EXT | C2 | hh ll | 4 | |
IX2 | D2 | ee ff | 5 | ||||||
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| IX1 | E2 | ff | 4 | |
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| IX | F2 |
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— | — | — | — | 1 | INH | 99 |
| 2 | |
— | 1 | — | — | — | INH | 9B |
| 2 | |
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| DIR | B7 | dd | 4 | |
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| EXT | C7 | hh ll | 5 | |
— | — | ↕ | ↕ | — | IX2 | D7 | ee ff | 6 | |
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| IX1 | E7 | ff | 5 | |
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| IX | F7 |
| 4 | |
— | 0 | — | — | — | INH | 8E |
| 2 | |
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| DIR | BF | dd | 4 | |
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| EXT | CF | hh ll | 5 | |
— | — | ↕ | ↕ | — | IX2 | DF | ee ff | 6 | |
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| IX1 | EF | ff | 5 | |
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| IX | FF |
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| IMM | A0 | ii | 2 | |
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| DIR | B0 | dd | 3 | |
— | — | ↕ | ↕ | ↕ | EXT | C0 | hh ll | 4 | |
IX2 | D0 | ee ff | 5 | ||||||
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| IX1 | E0 | ff | 4 | |
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| IX | F0 |
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— | 1 | — | — | — | INH | 83 |
| 10 | |
— | — | — | — | — | INH | 97 |
| 2 | |
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General Release Specification |
| MC68HC05RC16 — Rev. 3.0 |
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100 | Instruction Set | MOTOROLA |