Resets

Internal Resets

5.5.2.5 COP Register

The COP register is shared with the LSB of an unimplemented user interrupt vector as shown in Figure 5-3. Reading this location returns whatever user data has been programmed at this location. Writing a zero to the COPR bit in this location clears the COP watchdog timer.

Address:

$3FF0

 

 

 

 

 

 

 

 

BIt 7

6

5

4

3

2

1

Bit 0

 

 

 

 

 

 

 

 

 

Read:

X

X

X

X

X

X

X

X

 

 

 

 

 

 

 

 

 

Write:

 

 

 

 

 

 

 

COPR

 

 

 

 

 

 

 

 

 

Reset:

—

—

—

—

—

—

—

0

 

 

= Unimplemented

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5-3. COP Watchdog Timer Location

5.5.3 Illegal Address

An illegal address reset is generated when the CPU attempts to fetch an instruction from I/O address space ($0000 to $001F).

MC68HC05RC16 — Rev. 3.0

 

General Release Specification

 

 

 

MOTOROLA

Resets

51