Instruction Set

Instruction Set Summary

Table 10-6. Instruction Set Summary (Continued)

 

 

 

Effect on

Address Mode

Opcode

Operand

Cycles

Source

Operation

Description

 

CCR

 

 

 

 

Form

 

 

 

 

 

 

 

 

 

 

 

H

I

N

Z

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TST opr

 

 

 

 

 

 

 

DIR

3D

dd

4

 

 

 

 

 

 

 

 

TSTA

 

 

 

 

 

 

 

INH

4D

 

3

TSTX

Test Memory Byte for Negative or Zero

(M) – $00

—

—

↕

↕

—

INH

5D

 

3

TST opr,X

 

 

 

 

 

 

 

IX1

6D

ff

5

TST ,X

 

 

 

 

 

 

 

IX

7D

 

4

 

 

 

 

 

 

 

 

 

 

 

 

TXA

Transfer Index Register to Accumulator

A ← (X)

—

—

—

—

—

INH

9F

 

2

 

 

 

 

 

 

 

 

 

 

 

 

WAIT

Stop CPU Clock and Enable Interrupts

 

—

0￿

—

—

—

INH

8F

 

2

 

 

 

 

 

 

 

 

 

 

 

 

A

Accumulator

opr

Operand (one or two bytes)

C

Carry/borrow flag

PC

Program counter

CCR

Condition code register

PCH

Program counter high byte

dd

Direct address of operand

PCL

Program counter low byte

dd rr

Direct address of operand and relative offset of branch instruction

REL

Relative addressing mode

DIR

Direct addressing mode

rel

Relative program counter offset byte

ee ff

High and low bytes of offset in indexed, 16-bit offset addressing

rr

Relative program counter offset byte

EXT

Extended addressing mode

SP

Stack pointer

ff

Offset byte in indexed, 8-bit offset addressing

X

Index register

H

Half-carry flag

Z

Zero flag

hh ll

High and low bytes of operand address in extended addressing

#

Immediate value

I

Interrupt mask

∧

Logical AND

ii

Immediate operand byte

∨

Logical OR

IMM

Immediate addressing mode

⊕

Logical EXCLUSIVE OR

INH

Inherent addressing mode

( )

Contents of

IX

Indexed, no offset addressing mode

–( )

Negation (two’s complement)

IX1

Indexed, 8-bit offset addressing mode

←

Loaded with

IX2

Indexed, 16-bit offset addressing mode

?

If

M

Memory location

:

Concatenated with

N

Negative flag

↕

Set or cleared

n

Any bit

—

Not affected

MC68HC05RC16 — Rev. 3.0

 

General Release Specification

 

 

 

MOTOROLA

Instruction Set

101