Parallel Input/Output (I/O)

7.4 Port B

Port B is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The address of the port B data register is $0001 and the data direction register (DDR) is at address $0005. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Each of the port B pins has a mask programmable pullup device that can be enabled. When the pullup device is enabled, this pin will become an interrupt pin also. The edge or edge and level sensitivity of the IRQ pin also will pertain to the enabled port B pins. Care needs to be taken when using port B pins that have the pullup enabled. Before switching from an output to an input, the data should be preconditioned to a logic one or the I bit should be set in the condition code register to prevent an interrupt from occurring. The EIMSK bit in the CMT MCSR register can be used to mask port B keyscan and external interrupts (IRQ).

NOTE: When a port B pin is configured as an output, it’s corresponding keyscan interrupt is disabled, regardless of it’s mask option.

VDD

VDD

 

 

 

DISABLED

MASK OPTION (PB7PU)

 

 

 

 

DDR BIT

 

 

 

ENABLED

 

 

PB7

 

 

 

 

 

NORMAL PORT CIRCUITRY

IRQEN

TO INTERRUPT

 

IRQ

LOGIC

 

AS SHOWN IN FIGURE 7-2

 

 

FROM ALL OTHER PORT B PINS

Figure 7-1. Port B Pullup Option

7.5 Port C

Port C is an 8-bit bidirectional port (PC0–PC7) which does not share any of its pins with other subsystems. The port C data register is at $0003 and the data direction register (DDR) is at $0006. Reset does not affect the data register, but clears the data direction register, thereby returning

General Release Specification

 

MC68HC05RC16 — Rev. 3.0

 

 

 

58

Parallel Input/Output (I/O)

MOTOROLA