Instruction Set
10.5 Instruction Set Summary
Table
Source | Operation | |
Form | ||
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ADC #opr
ADC opr
ADC opr
Add with Carry
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
Add without Carry
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
Logical AND
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLXArithmetic Shift Left (Same as LSL) ASL opr,X
ASL ,X
ASR opr
ASRA
ASRXArithmetic Shift Right
ASR opr,X
ASR ,X
BCC rel | Branch if Carry Bit Clear |
BCLR n opr | Clear Bit n |
BCS rel | Branch if Carry Bit Set (Same as BLO) |
BEQ rel | Branch if Equal |
BHCC rel | Branch if |
BHCS rel | Branch if |
BHI rel | Branch if Higher |
BHS rel | Branch if Higher or Same |
Description
A ← (A) + (M) + (C)
A ← (A) + (M)
A ← (A) ∧ (M)
C
0
b7b0
C
b7b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
PC ← (PC) + 2 + rel ? C ∨ Z = 0
PC ← (PC) + 2 + rel ? C = 0
Effect on | Address Mode | Opcode | Operand | |||||
| CCR |
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H | I | N | Z | C |
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| IMM | A9 | ii | |
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| DIR | B9 | dd | |
↕ | — | ↕ | ↕ | ↕ | EXT | C9 | hh ll | |
IX2 | D9 | ee ff | ||||||
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| IX1 | E9 | ff | |
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| IX | F9 |
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| IMM | AB | ii | |
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| DIR | BB | dd | |
↕ | — | ↕ | ↕ | ↕ | EXT | CB | hh ll | |
IX2 | DB | ee ff | ||||||
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| IX1 | EB | ff | |
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| IX | FB |
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| IMM | A4 | ii | |
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| DIR | B4 | dd | |
— | — | ↕ | ↕ | — | EXT | C4 | hh ll | |
IX2 | D4 | ee ff | ||||||
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| IX1 | E4 | ff | |
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| IX | F4 |
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| DIR | 38 | dd | |
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| INH | 48 |
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— | — | ↕ | ↕ | ↕ | INH | 58 |
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| IX1 | 68 | ff | |
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| IX | 78 |
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| DIR | 37 | dd | |
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| INH | 47 |
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— | — | ↕ | ↕ | ↕ | INH | 57 |
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| IX1 | 67 | ff | |
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| IX | 77 |
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— | — | — | — | — | REL | 24 | rr | |
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| DIR (b0) | 11 | dd | |
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| DIR (b1) | 13 | dd | |
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| DIR (b2) | 15 | dd | |
— | — | — | — | — | DIR (b3) | 17 | dd | |
DIR (b4) | 19 | dd | ||||||
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| DIR (b5) | 1B | dd | |
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| DIR (b6) | 1D | dd | |
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| DIR (b7) | 1F | dd | |
— | — | — | — | — | REL | 25 | rr | |
— | — | — | — | — | REL | 27 | rr | |
— | — | — | — | — | REL | 28 | rr | |
— | — | — | — | — | REL | 29 | rr | |
— | — | — | — | — | REL | 22 | rr | |
— | — | — | — | — | REL | 24 | rr | |
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Cycles
2
3
4
5
4
3
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
3
5
5
5
5
5
5
5
5
3
3
3
3
3
3
General Release Specification |
| MC68HC05RC16 — Rev. 3.0 |
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96 | Instruction Set | MOTOROLA |