Carrier Modulator Transmitter (CMT)

Carrier Generator

Address:

$0013

 

 

 

 

 

 

 

 

 

Bit 7

6

5

4

3

2

1

Bit 0

Read:

 

 

 

 

 

 

 

 

 

0

 

0

SL5

SL4

SL3

SL2

SL1

SL0

Write:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset:

0

 

0

U

U

U

U

U

U

 

U = Unaffected

 

 

 

 

 

 

 

Figure 9-6. Carrier Generator Data Register CLR2

PH0–PH5 and PL0–PL5 — Primary Carrier High and Low Time Data

Values

When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is always selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the secondary register pair are alternately selected under control of the modulator. The primary carrier high and low time values are undefined out of reset. These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results.

NOTE: Writing to CHR1 to update PH0–PH5 or to CLR1 to update PL0–PL5 will also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear, the IRO latch value appears on the IRO output pin. Care should be taken that bit 7 of the data to be written to CHR1 or CHL1 should contain the desired state of the IRO latch.

SH0–SH5 and SL0–SL5 — Secondary Carrier High and Low Time Data

Values

When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is never selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the secondary register pair are alternately selected under control

MC68HC05RC16 — Rev. 3.0

 

General Release Specification

 

 

 

MOTOROLA

Carrier Modulator Transmitter (CMT)

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