General Release Specification — MC68HC05RC16

Section 7. Parallel Input/Output (I/O)

7.1 Contents

7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

7.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

7.6 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

7.2 Introduction

In user mode, 20 lines (in 28-pin PDIP or SOIC) or 24 lines (in 44-lead PLCC) are arranged as three 8-bit I/O ports. These ports are programmable as either inputs or outputs under software control of the data direction registers.

NOTE: To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register.

7.3 Port A

Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.

MC68HC05RC16 — Rev. 3.0

 

General Release Specification

 

 

 

MOTOROLA

Parallel Input/Output (I/O)

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