Carrier Modulator Transmitter (CMT)

9.4 Carrier Generator

The carrier signal is generated by counting a predetermined number of input clocks (500 ns for a 2-MHz oscillator) for both the carrier high time and the carrier low time. The period is determined by the total number of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted. The high and low time values are user programmable and are held in two registers. An alternate set of high/low count values is held in another set of registers to allow the generation of dual frequency FSK (frequency shift keying) protocols without CPU intervention. The MCGEN bit in the MCSR must be set and the BASE bit in the MCSR must be cleared to enable carrier generator clocks. The block diagram is shown in Figure 9-2.

SECONDARY HIGH COUNT REGISTER

PRIMARY HIGH COUNT REGISTER

fOSC

BASE

CONTROL

CLK

=?

6-BIT UP COUNTER

SELECT CONTROL

MODE

MODULATOR/

CARRIER GENERATOR ENABLE

CARRIER OUT

CLOCK AND OUTPUT

CLR

=?

SECONDARY LOW COUNT REGISTER PRIMARY LOW COUNT REGISTER

COUNT REGISTER

PRIMARY/ SECONDARY SELECT

Figure 9-2. Carrier Generator Block Diagram

General Release Specification

 

MC68HC05RC16 — Rev. 3.0

 

 

 

70

Carrier Modulator Transmitter (CMT)

MOTOROLA