MOTOROLA

MC68HC05RC16

 

0.3 .Rev —

Resets

47

Specification Release General

VDD

0 V

> VPOR 4

OSC12

4064 tCYC

tCYC

INTERNAL

PROCESSOR

CLOCK1

INTERNAL

 

 

 

 

 

 

 

 

 

ADDRESS

3FFE

3FFF

NEW PC NEW PC

3FFE

3FFE

3FFE

3FFE

3FFF

NEW PC NEW PC

BUS1

 

 

 

 

 

 

 

 

 

INTERNAL

NEW

NEW

OP

 

 

 

 

 

OP

DATA

 

 

 

PCH

PCL

BUS1

PCH

PCL

CODE

 

 

 

 

 

CODE

 

 

 

 

tRL

 

 

 

 

 

RESET5

 

 

 

3

 

 

 

 

 

NOTES:

1.Internal timing signal and bus information are not available externally.

2.OSC1 line is not meant to represent frequency. It is only used to represent time.

3.The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.

4.VDD must fall to a level lower than VPOR to be recognized as a power-on reset.

5.The LPRST pin resets the CPU like RESET. However, 4064 POR cycles are executed first, before the reset vector address appears on the internal address bus. (See 5.4 Low-Power External Reset (LPRST).)

Figure 5-2. Reset and POR Timing Diagram

(RESET) Reset External

Resets